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1. (WO2018180022) PULSE POSITION MODULATION CIRCUIT
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Pub. No.: WO/2018/180022 International Application No.: PCT/JP2018/006037
Publication Date: 04.10.2018 International Filing Date: 20.02.2018
IPC:
H04L 25/49 (2006.01) ,H03K 5/134 (2014.01)
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
25
Baseband systems
38
Synchronous or start-stop systems, e.g. for Baudot code
40
Transmitting circuits; Receiving circuits
49
using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels
[IPC code unknown for H03K 5/134]
Applicants: FUJITSU LIMITED[JP/JP]; 1-1, Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-shi, Kanagawa 2118588, JP
Inventors: SOGA, Ikuo; JP
OISHI, Kazuaki; JP
MATSUMURA, Hiroshi; JP
KAWANO, Yoichi; JP
NAKASHA, Yasuhiro; JP
Agent: MUKOUYAMA, Naoki; JP
Priority Data:
2017-06339128.03.2017JP
Title (EN) PULSE POSITION MODULATION CIRCUIT
(FR) CIRCUIT DE MODULATION DE POSITION D'IMPULSION
(JA) パルス位置変調回路
Abstract:
(EN) [Problem] To provide a pulse position modulation circuit capable of suppressing variations in delay time. [Solution] This pulse position modulation circuit is provided with: a delay path that comprises a plurality of delay devices connected in series, wherein a clock passes through the plurality of delay devices; and a switching circuit that, in accordance with input data, switches the time by which the clock is delayed in each of the plurality of delay devices. For example, in accordance with the input data the switching circuit switches a control signal for controlling the time by which the clock is delayed in each of the plurality of delay devices. For example, each of the plurality of delay devices comprises a plurality of control paths, and the switching circuit selects, in accordance with the input data, a path from among the plurality of control paths controlling the time by which the clock is delayed in accordance with the control signal.
(FR) [Problème] Fournir un circuit de modulation de position d'impulsion capable de supprimer les variations de temps de retard. La solution selon l'invention porte sur un circuit de modulation de position d'impulsion qui comprend : un chemin à retard qui comprend une pluralité de dispositifs à retard reliés en série, une horloge passant à travers la pluralité de dispositifs à retard; et un circuit de commutation qui, en fonction de données d'entrée, commute l'heure à laquelle l'horloge est retardée dans chacun de la pluralité de dispositifs à retard. Par exemple, conformément aux données d'entrée, le circuit de commutation commute un signal de commande pour commander l'heure à laquelle l'horloge est retardée dans chacun de la pluralité de dispositifs à retard. Par exemple, chacun de la pluralité de dispositifs à retard comprend une pluralité de chemins de commande, et le circuit de commutation sélectionne, en fonction des données d'entrée, un chemin parmi la pluralité de chemins de commande commandant l'heure à laquelle l'horloge est retardée en fonction du signal de commande.
(JA) 【課題】遅延時間のばらつきを抑制できるパルス位置変調回路を提供すること。 【解決手段】直列に接続された複数の遅延器を有し、クロックが前記複数の遅延器を通過する遅延経路と、前記クロックが前記複数の遅延器のそれぞれで遅延する時間を入力データに応じて切り替える切り替え回路とを備える、パルス位置変調回路。例えば、前記切り替え回路は、前記クロックが前記複数の遅延器のそれぞれで遅延する時間を制御する制御信号を前記入力データに応じて切り替える。例えば、前記複数の遅延器のそれぞれは、複数の制御経路を有し、前記切り替え回路は、前記クロックが遅延する時間を前記制御信号に応じて制御する経路を、前記複数の制御経路の中から前記入力データに応じて選択する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)