WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Options
Query Language
Stem
Sort by:
List Length
Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2018180010) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/180010 International Application No.: PCT/JP2018/005924
Publication Date: 04.10.2018 International Filing Date: 20.02.2018
IPC:
H01L 21/82 (2006.01) ,H01L 21/822 (2006.01) ,H01L 27/04 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
Applicants: SOCIONEXT INC.[JP/JP]; 2-10-23 Shin-Yokohama, Kohoku-Ku, Yokohama-shi, Kanagawa 2220033, JP
Inventors: ITO Chika; --
SOBUE Isaya; --
Agent: MAEDA & PARTNERS; Shin-Daibiru Bldg. 23F, 2-1, Dojimahama 1-chome, Kita-ku, Osaka-shi, Osaka 5300004, JP
Priority Data:
2017-06456829.03.2017JP
Title (EN) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
(FR) DISPOSITIF DE CIRCUIT INTÉGRÉ À SEMI-CONDUCTEUR
(JA) 半導体集積回路装置
Abstract:
(EN) Provided is a semiconductor integrated circuit device with IO cells disposed therein, wherein power supply voltage drop is suppressed by using multilayer wiring. Power supply wires (41a, 41b, and 41c) formed in a plurality of wiring layers are extended in an X-direction which is the same direction in which IO cells (10) are arranged. In a region of a power supply IO cell (21), a power supply wire (51) extending in a Y-direction is arranged on a wiring layer where the power supply wire (41b) is not formed, and at both ends in the X-direction, wiring pieces (61a, 61b) are arranged at the same position in the Y-direction as the power supply wire (41b) formed in a region of a signal IO cell (11).
(FR) L'invention concerne un dispositif de circuit intégré à semi-conducteur avec des cellules IO disposées à l'intérieur de celui-ci, la chute de tension d'alimentation électrique étant supprimée à l'aide d'un câblage multicouche. Des fils d'alimentation électrique (41a, 41b, et 41c) formés dans une pluralité de couches de câblage s'étendent dans une direction X qui est la même direction dans laquelle des cellules IO (10) sont agencées. Dans une région d'une cellule IO d'alimentation électrique (21), un fil d'alimentation électrique (51) s'étendant dans une direction Y est disposé sur une couche de câblage où le fil d'alimentation électrique (41b) n'est pas formé, et aux deux extrémités dans la direction X, des pièces de câblage (61a, 61b) sont agencées à la même position dans la direction Y que le fil d'alimentation électrique (41b) formé dans une région d'une cellule IO de signal (11).
(JA) IOセルが配置された半導体集積回路装置について、多層配線を利用して電源電圧降下を抑制可能にする。複数の配線層に形成された電源配線(41a,41b,41c)が、IOセル(10)の並びと同じX方向に延びている。電源IOセル(21)の領域において、電源配線(41b)が形成されていない配線層に、Y方向に延びる電源配線(51)が配置されており、かつ、X方向における両端において、Y方向における、信号IOセル(11)の領域に形成された電源配線(41b)と同じ位置に、配線片(61a,61b)が配置されている。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)