Some content of this application is unavailable at the moment.
If this situation persists, please contact us atFeedback&Contact
1. (WO2018179890) INSPECTION SYSTEM, WAFER MAP DISPLAY, WAFER MAP DISPLAY METHOD, AND COMPUTER PROGRAM
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2018/179890 International Application No.: PCT/JP2018/004408
Publication Date: 04.10.2018 International Filing Date: 08.02.2018
IPC:
H01L 21/66 (2006.01) ,G01R 31/26 (2014.01) ,G01R 31/28 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
66
Testing or measuring during manufacture or treatment
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
26
Testing of individual semiconductor devices
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28
Testing of electronic circuits, e.g. by signal tracer
Applicants:
東京エレクトロン株式会社 TOKYO ELECTRON LIMITED [JP/JP]; 東京都港区赤坂五丁目3番1号 3-1 Akasaka 5-chome, Minato-ku, Tokyo 1076325, JP
Inventors:
内田 伸 UCHIDA Shin; JP
加賀美 徹也 KAGAMI Tetsuya; JP
Agent:
高山 宏志 TAKAYAMA Hiroshi; JP
Priority Data:
2017-06704730.03.2017JP
Title (EN) INSPECTION SYSTEM, WAFER MAP DISPLAY, WAFER MAP DISPLAY METHOD, AND COMPUTER PROGRAM
(FR) SYSTÈME D'INSPECTION, AFFICHAGE DE CARTE DE TRANCHE, PROCÉDÉ D'AFFICHAGE DE CARTE DE TRANCHE ET PROGRAMME INFORMATIQUE
(JA) 検査システム、ウエハマップ表示器、ウエハマップ表示方法、およびコンピュータプログラム
Abstract:
(EN) An inspection system (100) is provided with a prober (200) and a tester (300). The tester (300) comprises: a plurality of tester module boards (33) on which a plurality of LSIs respectively corresponding to a plurality of devices under test (DUT) are mounted; a display unit (44) which displays a wafer map indicating inspection results of the plurality of DUTs and/or a self-diagnosis result of the tester (300); and a tester control unit (35) which includes a wafer map write application (60) for writing the wafer map displayed on the display unit (44). The wafer map write application (60) causes the inspection results and/or the self-diagnosis result to be displayed for each of the plurality of DUTs in a stepwise manner. In the wafer map, the plurality of DUTs are respectively tied with the plurality of LSIs mounted on the plurality of tester module boards (33).
(FR) L'invention concerne un système d'inspection (100) comprenant une sonde (200) et un testeur (300). Le testeur (300) comprend : une pluralité de cartes de module de testeur (33) sur lesquelles une pluralité de LSI correspondant respectivement à une pluralité de dispositifs en cours de test (DUT) sont montés; une unité d'affichage (44) qui affiche une carte de tranche indiquant des résultats d'inspection de la pluralité de DUT et/ou un résultat d'auto-diagnostic du testeur (300); et une unité de commande de testeur (35) qui comprend une application d'écriture de carte de tranche (60) pour écrire la carte de tranche affichée sur l'unité d'affichage (44). L'application d'écriture de carte de tranche (60) fait que les résultats d'inspection et/ou le résultat d'auto-diagnostic sont affichés pour chacun de la pluralité de DUT pas à pas. Dans la carte de tranche, la pluralité de DUT est respectivement liée à la pluralité de LSI montés sur la pluralité de cartes de module de testeur (33).
(JA) 検査システム(100)は、プローバ(200)と、テスタ(300)とを備える。テスタ(300)は、複数のDUTの各々に対応するLSIを複数搭載した複数のテスタモジュールボード(33)と、複数のDUTの検査結果および/またはテスタ(300)の自己診断結果を示したウエハマップを表示する表示部(44)、および表示部(44)に表示するウエハマップを描画するウエハマップ描画アプリケーション(60)を有するテスタ制御部(35)とを有し、ウエハマップ描画アプリケーション(60)は、検査結果および/または自己診断結果を複数のDUTの各々に段階的に表示するとともに、ウエハマップにおける複数のDUTの各々が、複数のテスタモジュールボード(33)に搭載された複数のLSIの各々に紐付けられている。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)