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1. (WO2018179177) MOUNTING METHOD, MOUNTING DEVICE, AND MANUFACTURING DEVICE
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Pub. No.: WO/2018/179177 International Application No.: PCT/JP2017/013041
Publication Date: 04.10.2018 International Filing Date: 29.03.2017
IPC:
G09F 9/00 (2006.01) ,H01L 21/60 (2006.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
三保谷 拓史 MIHOTANI, Takushi; --
塩田 素二 SHIOTA, Motoji; --
Agent:
特許業務法人HARAKENZO WORLD PATENT & TRADEMARK HARAKENZO WORLD PATENT & TRADEMARK; 大阪府大阪市北区天神橋2丁目北2番6号 大和南森町ビル Daiwa Minamimorimachi Building, 2-6, Tenjinbashi 2-chome Kita, Kita-ku, Osaka-shi, Osaka 5300041, JP
Priority Data:
Title (EN) MOUNTING METHOD, MOUNTING DEVICE, AND MANUFACTURING DEVICE
(FR) PROCÉDÉ DE MONTAGE, DISPOSITIF DE MONTAGE ET DISPOSITIF DE FABRICATION
(JA) 実装方法、実装装置、および製造装置
Abstract:
(EN) A mounting method according to the present invention comprises: a pressing step for generating a pressing force to press an inactive area (NA) against a backup stage (202); and a press-bond process for pressing and bonding an electronic circuit board (60) to a terminal (TM) after the inactive area is pressed against the backup stage by the pressing force generated in the pressing step.
(FR) Un procédé de montage selon la présente invention comporte: une étape de pression visant à générer une force de pression servant à plaquer une zone inactive (NA) contre une platine (202) de soutien; et un processus de collage sous pression visant à presser et à coller une carte (60) à circuit électronique à un terminal (TM) après que la zone inactive a été plaquée contre la platine de soutien par la force de pression générée lors de l'étape de pression.
(JA) 実装方法は、バックアップステージ(202)に対して非アクティブ領域(NA)を押し付ける押圧力を発生させる押圧工程と、押圧工程にて発生させた押圧力により非アクティブ領域がバックアップステージに対して押し付けられた後、端子(TM)に電子回路基板(60)を圧着する圧着工程と、を含む。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)