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1. (WO2018179121) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2018/179121 International Application No.: PCT/JP2017/012839
Publication Date: 04.10.2018 International Filing Date: 29.03.2017
IPC:
H01L 29/786 (2006.01) ,G02F 1/1368 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
1368
in which the switching element is a three-electrode device
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
岡部 達 OKABE, Tohru; --
田中 哲憲 TANAKA, Tetsunori; --
家根田 剛士 YANEDA, Takeshi; --
Agent:
特許業務法人HARAKENZO WORLD PATENT & TRADEMARK HARAKENZO WORLD PATENT & TRADEMARK; 大阪府大阪市北区天神橋2丁目北2番6号 大和南森町ビル Daiwa Minamimorimachi Building, 2-6, Tenjinbashi 2-chome Kita, Kita-ku, Osaka-shi, Osaka 5300041, JP
Priority Data:
Title (EN) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET PROCÉDÉ DE FABRICATION D'UN DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置および半導体装置の製造方法
Abstract:
(EN) A semiconductor device (10) provided to a pixel circuit of a display apparatus (1) includes, sequentially from the lower side: a substrate (11); a LTPS layer (135SLA); a first gate insulating layer (14); a first metal layer (145GA, 145GB); a first planarization layer (15); a second insulating layer (16); an oxide semiconductor layer (165SLB); a second metal layer (165SB, 165DB), a passivation layer (17); and a third metal layer (165CA). A gate electrode (145GA) of a LTPS-TFT (10A) and a gate electrode (145GB) of an oxide semiconductor TFT (10B) are formed by the first metal layer.
(FR) L'invention concerne un dispositif à semi-conducteur (10) disposé sur un circuit de pixel d'un appareil d'affichage (1) comprenant, de manière séquentielle à partir du côté inférieur : un substrat (11); une couche LTPS (135SLA); une première couche d'isolation de grille (14); une première couche métallique (145GA, 145GB); une première couche de planarisation (15); une seconde couche d'isolation (16); une couche semi-conductrice d'oxyde (165SLB); une seconde couche métallique (165SB, 165DB), une couche de passivation (17); et une troisième couche métallique (165CA). Une électrode de grille (145GA) d'un LTPS-TFT (10A) et une électrode de grille (145GB) d'un TFT à semi-conducteur à oxyde (10B) sont formées par la première couche métallique.
(JA) 表示装置(1)の画素回路に設けられる半導体装置(10)は、下側から順に、基板(11)と、LTPS層(135SLA)と、第1ゲート絶縁層(14)と、第1金属層(145GA・145GB)と、第1平坦化層(15)と、第2ゲート絶縁層(16)と、酸化物半導体層(165SLB)半導体層と、第2金属層(165SB・165DB)と、パッシベーション層(17)と、第3金属層(165CA)と、を含む。LTPS-TFT(10A)のゲート電極(145GA)と酸化物半導体TFT(10B)のゲート電極(145GB)とは、第1金属層により形成される。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)