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1. (WO2018178657) ELECTRONIC STRUCTURES AND THEIR METHODS OF MANUFACTURE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/178657 International Application No.: PCT/GB2018/050805
Publication Date: 04.10.2018 International Filing Date: 27.03.2018
IPC:
H01L 27/06 (2006.01) ,H01L 21/822 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
06
including a plurality of individual components in a non-repetitive configuration
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
Applicants: PRAGMATIC PRINTING LTD[GB/GB]; National Centre for Printable Electronics Thomas Wright Way NETPark SEDGEFIELD Durham TS21 3FG, GB
Inventors: PRICE, Richard; GB
RAMSDALE, Catherine; GB
COBB, Brian Hardy; GB
ALKHALIL, Feras; GB
Agent: HGF LIMITED; Document Handling (HGF) - York 1 City Walk Leeds LS11 9DX, GB
Priority Data:
1705270.531.03.2017GB
Title (EN) ELECTRONIC STRUCTURES AND THEIR METHODS OF MANUFACTURE
(FR) STRUCTURES ÉLECTRONIQUES ET LEURS PROCÉDÉS DE FABRICATION
Abstract:
(EN) A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal. Methods of manufacturing such structures are also disclosed.
(FR) L'invention concerne une structure comprenant : un premier transistor à effet de champ (TEC) pourvu d'une première borne de source, d'une première borne de drain, d'une première couche ou d'un premier corps de matériau semi-conducteur agencé de façon à fournir un premier canal semi-conducteur connectant la première borne de source à la première borne de drain, et d'une borne de grille disposée par rapport au premier canal semi-conducteur de telle sorte qu'une conductivité du premier canal semi-conducteur peut être commandée par application d'une tension à la borne de grille ; et un second TEC pourvu d'une seconde borne de source, d'une seconde borne de drain, d'une seconde couche ou d'un second corps de matériau semi-conducteur agencé de façon à fournir un second canal semi-conducteur connectant la seconde borne de source à la seconde borne de drain, et la borne de grille, le second canal conducteur étant agencé par rapport à la borne de grille de telle sorte qu'une conductivité du second canal peut être commandée par application d'une tension à la borne de grille. L’invention concerne également des procédés de fabrication de telles structures.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)