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1. (WO2018177764) METHOD FOR PRODUCING LIGHT-EMITTING DIODE CHIPS AND LIGHT-EMITTING DIODE CHIP
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Pub. No.: WO/2018/177764 International Application No.: PCT/EP2018/056558
Publication Date: 04.10.2018 International Filing Date: 15.03.2018
IPC:
H01L 33/00 (2010.01) ,H01L 33/22 (2010.01) ,H01L 33/32 (2010.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
02
characterised by the semiconductor bodies
20
with a particular shape, e.g. curved or truncated substrate
22
Roughened surfaces, e.g. at the interface between epitaxial layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
02
characterised by the semiconductor bodies
26
Materials of the light emitting region
30
containing only elements of group III and group V of the periodic system
32
containing nitrogen
Applicants: OSRAM OPTO SEMICONDUCTORS GMBH[DE/DE]; Leibnizstr. 4 93055 Regensburg, DE
Inventors: DRAGO, Massimo; DE
FREY, Alexander; DE
HERTKORN, Joachim; DE
Agent: ZUSAMMENSCHLUSS NR. 175 - EPPING HERMANN FISCHER PATENTANWALTSGESELLSCHAFT MBH; Schloßschmidstr. 5 80639 München, DE
Priority Data:
10 2017 106 888.030.03.2017DE
Title (EN) METHOD FOR PRODUCING LIGHT-EMITTING DIODE CHIPS AND LIGHT-EMITTING DIODE CHIP
(FR) PROCÉDÉ DE FABRICATION DE PUCES DE DIODE ÉLECTROLUMINESCENTE ET PUCE DE DIODE ÉLECTROLUMINESCENTE
(DE) VERFAHREN ZUR HERSTELLUNG VON LEUCHTDIODENCHIPS UND LEUCHTDIODENCHIP
Abstract:
(EN) The method is designed for producing light-emitting diode chips and comprises the following steps: A) providing a growth substrate (1), C) creating a structural layer (3), in particular with a multiplicity of pyramidal structural elements (33), wherein the structural layer (3) comprises A1x1Ga1-x1-y1Iny1N with yl ≥ 0.5, D) creating a top layer (4) on the structural layer (3), wherein the top layer (4) faithfully replicates the structural layer (3) and comprises A1x2Ga1-x2-y2Iny2N with x2 ≥ 0.6, E) creating a planarizing layer (5) on the top layer (4), wherein a side of the finished planarizing layer (5) that is facing away from the growth substrate (1) is planar and the planarizing layer (5) comprises A1x3Ga1-x3-y3lny3N with x3 + y3 ≥ 0.2, and F) growing a series of functional layers (7) for radiation generation on the planarizing layer (5).
(FR) L'invention concerne un procédé de fabrication de puces de diode électroluminescente qui comprend les étapes suivantes : A) fournir un substrat de croissance (1), C) réaliser une couche structurelle (3), pourvue en particulier d'une pluralité d'éléments structurels pyramidaux (33), la couche structurelle (3) étant constituée de A1x1Ga1-x1-y1Iny1N avec yl ≥ 0,5, D) réaliser une couche de recouvrement (4) sur la couche structurelle (3), la couche de recouvrement (4) reproduisant la forme de la couche structurelle (3) et étant constituée de A1x2Ga1-x2-y2Iny2N avec x2 ≥ 0,6, E) réaliser une couche de planarisation (5) sur la couche de recouvrement (4), un côté, opposé au substrat de croissance (1), de la couche de planarisation fini (5) étant plan et la couche de planarisation (5) étant constitué de A1x3Ga1-x3-y3lny3N avec x3 + y3 ≥ 0,2 et F) faire croître une succession de couches fonctionnelles (7) pour générer un rayonnement sur la couche de planarisation (5).
(DE) Das Verfahren ist zur Herstellung von Leuchtdiodenchips eingerichtet und weist die folgenden Schritte auf: A) Bereitstellen eines Aufwachssubstrats (1), C) Erzeugen einer Strukturschicht (3), insbesondere mit einer Vielzahl von pyramidenförmigen Strukturelementen (33), wobei die Strukturschicht (3) aus A1x1Ga1-x1-y1Iny1N ist mit yl ≥ 0,5, D) Erzeugen einer Deckschicht (4) auf der Strukturschicht (3), wobei die Deckschicht (4) die Strukturschicht (3) formtreu nachformt und aus A1x2Ga1-x2-y2Iny2N ist mit x2 ≥ 0, 6, E) Erzeugen einer Planarisierungsschicht (5) auf der Deckschicht (4), wobei eine dem Aufwachssubstrat (1) abgewandte Seite der fertigen Planarisierungsschicht (5) eben ist und die Planarisierungsschicht (5) aus A1x3Ga1-x3-y3lny3N ist mit x3 + y3 ≥ 0,2, und F) Wachsen einer Funktionsschichtenfolge (7) zur Strahlungserzeugung auf der Planarisierungsschicht (5).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: German (DE)
Filing Language: German (DE)