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1. (WO2018166264) PACKAGED CHIP AND PACKAGING METHOD
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Pub. No.: WO/2018/166264 International Application No.: PCT/CN2017/117764
Publication Date: 20.09.2018 International Filing Date: 21.12.2017
IPC:
H01L 23/492 (2006.01) ,H01L 21/50 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
492
Bases or plates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
Applicants:
深圳市江波龙电子有限公司 SHENZHEN LONGSYS ELECTRONICS CO., LIMITED [CN/CN]; 中国广东省深圳市 南山区科发路8号金融服务技术创新基地1栋8楼A、B、C、D、E、F1 A-B-C-D-E-F1, 8F, 1 Building, Financial Base, No.8, Kefa Road, High-Tech Park, Nanshan District Shenzhen, Guangdong 518000, CN
Inventors:
李志雄 LI, Zhixiong; CN
庞卫文 PANG, Weiwen; CN
何宏 HE, Hong; CN
胡宏辉 HU, Honghui; CN
Agent:
深圳市六加知识产权代理有限公司 LIUJIA CHINA IP LAW OFFICE; 中国广东省深圳市 南山区南海大道4050号上汽大厦207室 Room 207, Shangqi Building 4050# Nanhai Road, Nanshan District Shenzhen, Guangdong 518057, CN
Priority Data:
201710148504.114.03.2017CN
Title (EN) PACKAGED CHIP AND PACKAGING METHOD
(FR) PUCE ENCAPSULÉE ET PROCÉDÉ D'ENCAPSULATION
(ZH) 一种封装芯片及封装方法
Abstract:
(EN) The present application relates to the technical field of chip packaging. Provided are a packaged chip and a packaging method. The packaged chip comprises a printed circuit board, a chip provided on the upper surface of the printed circuit board, and a packaging encapsulant provided on the surface of the printed circuit board and used for packaging the chip. First solder balls are provided on the lower surface of the printed circuit board and at positions corresponding to the packaging encapsulant. The chip is fixed on the printed circuit board via second solder balls. A via is provided on the printed circuit board. The via is arranged below the chip. In the present application, the via is provided on the printed circuit board at a position corresponding to the chip, during secondary SMT, air between the chip and the printed circuit board is expelled through the via, thus preventing the phenomenon of the second solder balls bursting or the printed circuit board bulging, and increasing the yield of the packaged chip.
(FR) La présente invention se rapporte au domaine technique d'encapsulation de puce. L'invention concerne une puce encapsulée et un procédé d'encapsulation. La puce encapsulée comprend une carte de circuit imprimé, une puce disposée sur la surface supérieure de la carte de circuit imprimé, et un encapsulant d'encapsulation disposé sur la surface de la carte de circuit imprimé et utilisé pour encapsuler la puce. Des premières perles de soudure sont disposées sur la surface inférieure de la carte de circuit imprimé et à des positions correspondant à l'encapsulant d'encapsulation. La puce est fixée sur la carte de circuit imprimé par l'intermédiaire de secondes perles de soudure. Un trou d'interconnexion est prévu sur la carte de circuit imprimé. Le trou d'interconnexion est disposé au-dessous de la puce. Dans la présente invention, le trou d'interconnexion est disposé sur la carte de circuit imprimé à une position correspondant à la puce, pendant une SMT secondaire, de l'air entre la puce et la carte de circuit imprimé est expulsé par l'intermédiaire du trou d'interconnexion, ce qui permet d'empêcher le phénomène de rupture de la seconde perle de soudure ou de gonflement de la carte de circuit imprimé, et d'augmenter le rendement de la puce encapsulée.
(ZH) 本申请涉及芯片封装技术领域,提供了一种封装芯片及封装方法,所述封装芯片包括印刷电路板、设于所述印刷电路板上表面的芯片以及设于所述印刷电路板上表面用于封装所述芯片的封装胶体,所述印刷电路板下表面且与所述封装胶体对应处设有第一锡球,所述芯片通过第二锡球固定于所述印刷电路板上,所述印刷电路板上设有通孔,所述通孔位于所述芯片下方。本申请中,在印刷电路板上且对应于芯片处设置通孔,在二次SMT时,芯片与印刷电路板之间的空气由通孔中排出,从而避免第二锡球爆裂或者印刷电路板产生鼓包现象,提高了封装芯片的良品率。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)