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1. (WO2018166201) DATA READING METHOD, LOW-VOLTAGE DETECTION LOGIC CIRCUIT, INTEGRATED CIRCUIT AND CHIP

Pub. No.:    WO/2018/166201    International Application No.:    PCT/CN2017/106699
Publication Date: Fri Sep 21 01:59:59 CEST 2018 International Filing Date: Thu Oct 19 01:59:59 CEST 2017
IPC: G11C 16/22
Applicants: GREE ELECTRIC APPLIANCES, INC. OF ZHUHAI
珠海格力电器股份有限公司
Inventors: WEN, Langming
温浪明
CHEN, Heng
陈恒
YI, Dongbai
易冬柏
FANG, Li
方励
Title: DATA READING METHOD, LOW-VOLTAGE DETECTION LOGIC CIRCUIT, INTEGRATED CIRCUIT AND CHIP
Abstract:
A data reading method, low-voltage detection logic circuit, an integrated circuit and a chip. The data reading method comprises: upon receiving a request to read data within a non-volatile memory (NVM), reading a pre-burning area return value from a preset pre-burning area of the NVM (S101), wherein the pre-burning area is a storage space within the NVM which is sensitive to a low supply voltage, and the low supply voltage is a voltage which is lower than a supply voltage threshold; determining whether the pre-burning area return value is equal to a target preset value (S102); when the pre-burning area return value is equal to the target preset value, generating a first control signal, and sending the first control signal to an NVM controller to control the NVM controller to read the data within the NVM (S103). The method may increase the stability of reading data from NVMs, and prevent to the greatest extent the problem wherein data reading is unstable due to the power supply voltage of the NVM being in an abnormal state.