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1. (WO2018166024) METHOD FOR MANUFACTURING TFT AND METHOD FOR MANUFACTURING ARRAY SUBSTRATE
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Pub. No.: WO/2018/166024 International Application No.: PCT/CN2017/080406
Publication Date: 20.09.2018 International Filing Date: 13.04.2017
IPC:
H01L 21/336 (2006.01) ,H01L 21/28 (2006.01) ,H01L 29/786 (2006.01) ,H01L 21/77 (2017.01) ,H01L 27/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
Applicants:
深圳市华星光电技术有限公司 SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国广东省深圳市 光明新区塘明大道9-2号 No. 9-2, Tangming Rd, Guangming New District Shenzhen, Guangdong 518132, CN
Inventors:
蔡小龙 CAI, Xiaolong; CN
Agent:
深圳市威世博知识产权代理事务所(普通合伙) CHINA WISPRO INTELLECTUAL PROPERTY LLP.; 中国广东省深圳市 南山区高新区粤兴三道8号中国地质大学产学研基地中地大楼A806 Room A806 Zhongdi Building, China University of Geosciences Base, No. 8 Yuexing 3rd Road, High-Tech Industrial Estate, Nanshan District Shenzhen, Guangdong 518057, CN
Priority Data:
201710153568.015.03.2017CN
Title (EN) METHOD FOR MANUFACTURING TFT AND METHOD FOR MANUFACTURING ARRAY SUBSTRATE
(FR) PROCÉDÉ DE FABRICATION DE TRANSISTOR À COUCHES MINCES ET PROCÉDÉ DE FABRICATION DE SUBSTRAT DE MATRICE
(ZH) TFT的制造方法及阵列基板的制造方法
Abstract:
(EN) A method for manufacturing a TFT and a method for manufacturing an array substrate. The method comprises: forming, on a base substrate (20), transfer layers (212) that are provided alternately at intervals; forming, on the transfer layers, a metal layer (22) covering the base substrate; and carrying out a DIW demoulding process on the transfer layers, so as to strip the transfer layers and the metal layer above same from the base substrate, and keeping the metal layer, not provided above the transfer layers, on the base substrate, so as to form a metal electrode (23) of the TFT.
(FR) L’invention concerne un procédé de fabrication d’un transistor à couches minces et un procédé de fabrication d’un substrat de matrice. Le procédé consiste à : former, sur un substrat de base (20), des couches de transfert (212) qui sont disposées en alternance à intervalles ; former, sur les couches de transfert, d'une couche métallique (22) recouvrant le substrat de base ; et réaliser un processus de démoulage DIW sur les couches de transfert, de manière à dénuder les couches de transfert et la couche métallique au-dessus de celles-ci à partir du substrat de base, et conserver la couche métallique, non disposée au-dessus des couches de transfert, sur le substrat de base, de manière à former une électrode métallique (23) du transistor à couches minces.
(ZH) 一种TFT的制造方法及阵列基板的制造方法。在衬底基材(20)上形成交错间隔设置的中转层(212);在中转层上形成覆盖衬底基材的金属层(22);对中转层进行DIW脱膜制程,以将中转层及其上方的金属层从衬底基材上剥离,而未设置在中转层上方的金属层保留在衬底基材上而形成TFT的金属电极(23)。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)