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1. (WO2018165809) TRANSISTOR DEVICE WITH SINKER CONTACTS AND METHODS FOR MANUFACTURING THE SAME
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Pub. No.: WO/2018/165809 International Application No.: PCT/CN2017/076387
Publication Date: 20.09.2018 International Filing Date: 13.03.2017
IPC:
H01L 21/00 (2006.01) ,H01L 29/45 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
43
characterised by the materials of which they are formed
45
Ohmic electrodes
Applicants:
TEXAS INSTRUMENTS INCORPORATED [US/US]; P.O.Box 655474 Mail Station 3999 Dallas, TX 75243, US
TEXAS INSTRUMENTS JAPAN LIMITED [JP/JP]; 24-1, Nishi-Shinjuku 6-chome Shinjuku-Ku Tokyo 160-8366, JP (JP)
Inventors:
XIONG, Yufei; CN
YANG, Hong; US
CHISHOLM, Michael F.; US
LIU, Yunlong; CN
Agent:
JEEKAI & PARTNERS; Floor 15A, Building No. 5, GTFC Plaza 9 Guang'an Road, Fengtai District Beijing 100055, CN
Priority Data:
Title (EN) TRANSISTOR DEVICE WITH SINKER CONTACTS AND METHODS FOR MANUFACTURING THE SAME
(FR) DISPOSITIF DE TRANSISTOR COMPRENANT DES CONTACTS ÉLECTRIQUES ET PROCÉDÉS DE FABRICATION ASSOCIÉS
Abstract:
(EN) A device includes a semiconductor substrate (100); a buried layer (101); and a trench (128) with inner walls extending from the buried layer (101) to a surface of the semiconductor substrate (100), the trench (128) having sidewalls, a bottom wall, a barrier layer (134) including a titanium (Ti) layer covering the sidewalls and the bottom wall, and a filler including more than one layer of conductor material (130, 132) formed on the barrier layer (134).
(FR) L'invention concerne un dispositif comprenant un substrat semiconducteur (100); une couche enfouie (101); et une tranchée (128) avec des parois internes s'étendant à partir de la couche enfouie (101) jusqu'à une surface du substrat semiconducteur (100), la tranchée (128) ayant des parois latérales, une paroi inférieure, une couche barrière (134) comprenant une couche de titane (Ti) recouvrant les parois latérales et la paroi inférieure, et une charge comprenant plus d'une couche de matériau conducteur (130, 132) formée sur la couche barrière (134).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)