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1. (WO2018164759) GETTERING LAYER FORMATION IN A SUBSTRATE AND INTEGRATED CIRCUIT COMPRISING THE SUBSTRATE

Pub. No.:    WO/2018/164759    International Application No.:    PCT/US2017/068971
Publication Date: Fri Sep 14 01:59:59 CEST 2018 International Filing Date: Sat Dec 30 00:59:59 CET 2017
IPC: H01L 21/322
H01L 21/265
Applicants: QUALCOMM INCORPORATED
Inventors: LI, Xia
YANG, Bin
TAO, Gengming
Title: GETTERING LAYER FORMATION IN A SUBSTRATE AND INTEGRATED CIRCUIT COMPRISING THE SUBSTRATE
Abstract:
An integrated circuit (IC) device may include a substrate having an active device layer. The integrated circuit may also include a first defect layer. The first defect layer may have a first surface facing a backside of the active device layer. The integrated circuit may further include a second defect layer. The second defect layer may face a second surface opposite the first surface of the first defect layer.