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1. (WO2018164360) METHOD FOR MANUFACTURING COMPLIANT BUMP
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Pub. No.: WO/2018/164360 International Application No.: PCT/KR2017/015669
Publication Date: 13.09.2018 International Filing Date: 28.12.2017
IPC:
H01L 23/00 (2006.01) ,H01L 21/027 (2006.01) ,H01L 21/324 (2006.01) ,H01L 23/488 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
027
Making masks on semiconductor bodies for further photolithographic processing, not provided for in group H01L21/18 or H01L21/34165
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
324
Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
Applicants: LBSEMICON CO., LTD[KR/KR]; 138, Cheongbuksandan-ro, Cheongbuk-myeon Pyeongtaek-si Gyeonggi-do 17792, KR
Inventors: KWON, Jae Jin; KR
Agent: KIM, Nam Sik; KR
LEE, In Haeng; KR
KIM, Han; KR
Priority Data:
10-2017-002834406.03.2017KR
Title (EN) METHOD FOR MANUFACTURING COMPLIANT BUMP
(FR) PROCÉDÉ DE FABRICATION DE BOSSE SOUPLE
(KO) 컴플라이언트 범프의 제조방법
Abstract:
(EN) The present invention provides a method for manufacturing a compliant bump, the method comprising the steps of: preparing an electronic element comprising at least one conductive pad; forming an elastic resin layer on the electronic element; forming a photoresist layer on the elastic resin layer; subjecting the photoresist layer to a photolithography process so as to form a first photoresist pattern in an area spaced apart from the area in which the conductive pad is positioned; subjecting the first photoresist pattern to a baking process so as to form a second photoresist pattern, the sectional area of the lower end of the second photoresist pattern being larger than the sectional area of the upper end thereof; subjecting the elastic resin layer to an etching process using the second photoresist pattern as a mask so as to form an elastic resin pattern in an area spaced apart from the area in which the conductive pad is positioned, the sectional area of the lower end of the elastic resin pattern being larger than the sectional area of the upper end thereof; and forming a conductive wiring pattern that extends to the conductive pad while covering at least a part of the elastic resin pattern.
(FR) La présente invention concerne un procédé de fabrication d'une bosse souple, le procédé comprenant les étapes consistant à : préparer un élément électronique comprenant au moins un plot conducteur; former une couche de résine élastique sur l'élément électronique; former une couche de résine photosensible sur la couche de résine élastique; soumettre la couche de résine photosensible à un procédé de photolithographie de façon à former un premier motif de résine photosensible dans une zone espacée de la zone dans laquelle le plot conducteur est positionné; soumettre le premier motif de résine photosensible à un processus de cuisson de façon à former un second motif de résine photosensible, la section transversale de l'extrémité inférieure du second motif de résine photosensible étant plus grande que la section transversale de son extrémité supérieure; soumettre la couche de résine élastique à un processus de gravure à l'aide du second motif de résine photosensible en tant que masque de façon à former un motif de résine élastique dans une zone espacée de la zone dans laquelle le plot conducteur est positionné, la surface de section de l'extrémité inférieure du motif de résine élastique étant plus grande que la surface de section de son extrémité supérieure; et former un motif de câblage conducteur qui s'étend jusqu'au plot conducteur tout en recouvrant au moins une partie du motif de résine élastique.
(KO) 본 발명은 적어도 하나 이상의 도전성 패드를 구비하는 전자 소자를 준비하는 단계; 상기 전자 소자 상에 탄성 레진층을 형성하는 단계; 상기 탄성 레진층 상에 포토레지스트층을 형성하는 단계; 상기 포토레지스트층에 포토리소그래피 공정을 수행하여, 상기 도전성 패드가 위치하는 영역과 이격된 영역에 제 1 포토레지스트 패턴을 형성하는 단계; 상기 제 1 포토레지스트 패턴에 베이크 공정을 수행하여, 상단의 단면적 보다 하단의 단면적이 더 넓은 제 2 포토레지스 패턴을 형성하는 단계; 상기 제 2 포토레지스트 패턴을 마스크로 이용하여 상기 탄성 레진층에 식각공정을 수행하여, 상기 도전성 패드가 위치하는 영역과 이격된 영역에, 상단의 단면적 보다 하단의 단면적이 더 넓은 탄성 레진패턴을 형성하는 단계; 및 상기 탄성 레진패턴의 적어도 일부를 덮으면서 상기 도전성 패드까지 연장된 도전성 배선패턴을 형성하는 단계;를 포함하는 컴플라이언트 범프의 제조방법을 제공한다.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)