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1. (WO2018164359) BUMP STRUCTURE MANUFACTURING METHOD
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Pub. No.: WO/2018/164359 International Application No.: PCT/KR2017/015668
Publication Date: 13.09.2018 International Filing Date: 28.12.2017
IPC:
H01L 23/00 (2006.01) ,H01L 23/488 (2006.01) ,H01L 21/683 (2006.01) ,H01L 21/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67
Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
683
for supporting or gripping
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
Applicants:
엘비세미콘 주식회사 LBSEMICON CO., LTD [KR/KR]; 경기도 평택시 청북면 청북산단로 138 138, Cheongbuksandan-ro, Cheongbuk-myeon Pyeongtaek-si Gyeonggi-do 17792, KR
Inventors:
이진국 LEE, Jin Kuk; KR
Agent:
김남식 KIM, Nam Sik; KR
이인행 LEE, In Haeng; KR
김한 KIM, Han; KR
Priority Data:
10-2017-002834306.03.2017KR
Title (EN) BUMP STRUCTURE MANUFACTURING METHOD
(FR) PROCÉDÉ DE FABRICATION DE STRUCTURE DE BOSSE
(KO) 범프 구조체의 제조방법
Abstract:
(EN) The present invention provides a bump structure manufacturing method comprising: a first step of preparing a wafer comprising a plurality of chips, each of which includes a die pad, an under bump metal (UBM) layer on the die pad, and a bump pattern on the UBM layer; a second step of attaching a back grinding film to the upper surface of the wafer; a third step of grinding and removing the rear surface of the wafer by a predetermined thickness; a fourth step of forming a flexible material layer on a second rear surface of the wafer after the grinding and removing, followed by attaching a dicing tape including a ring frame to the second rear surface of the wafer; a fifth step of removing the back grinding film and then curing the flexible material layer; and a sixth step of performing a dicing process to divide the plurality of chips into individual chips.
(FR) La présente invention concerne un procédé de fabrication de structure de bosse comprenant : une première étape de préparation d'une tranche comprenant une pluralité de puces, dont chacune comprend une pastille de puce, une couche de métal sous bosse (UBM) sur la pastille de puce, et un motif de bosse sur la couche UBM ; une seconde étape de fixation d'un film de meulage arrière sur la surface supérieure de la tranche ; une troisième étape de meulage et de retrait de la surface arrière de la tranche d'une épaisseur prédéterminée ; une quatrième étape de formation d'une couche de matériau flexible sur une seconde surface arrière de la tranche après le meulage et le retrait, suivie par la fixation d'une bande de découpage en dés comprenant un cadre annulaire à la seconde surface arrière de la tranche ; une cinquième étape de retrait du film de meulage arrière puis de durcissement de la couche de matériau flexible ; et une sixième étape de réalisation d'un processus de découpage en dés destiné à diviser la pluralité de puces en puces individuelles.
(KO) 본 발명은 다이 패드(die pad), 상기 다이 패드 상의 UBM(Under Bump Metal)층 및 상기 UBM층 상의 범프패턴을 각각 구비하는 복수의 칩을 포함하는 웨이퍼를 준비하는 제 1 단계; 상기 웨이퍼의 상면에 백 그라인드(Back Grinding) 필름을 부착하는 제 2 단계; 상기 웨이퍼의 후면을 일부 두께만큼 그라인딩 제거하는 제 3 단계; 그라인딩 제거한 후의 상기 웨이퍼의 제 2 후면에 유연 물질층을 형성한 후 링 프레임을 구비하는 다이싱 테이프를 부착하는 제 4 단계; 상기 백 그라인드 필름을 제거한 후 상기 유연 물질층을 경화시키기 위하여 큐어링을 진행하는 제 5 단계; 및 상기 복수의 칩을 개별칩으로 분리하도록 다이싱 공정을 진행하는 제 6 단계;를 포함하는 범프 구조체의 제조방법을 제공한다.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)