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1. (WO2018164175) ADHESIVE TAPE FOR SEMICONDUCTOR PROCESSING
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Pub. No.: WO/2018/164175 International Application No.: PCT/JP2018/008737
Publication Date: 13.09.2018 International Filing Date: 07.03.2018
IPC:
H01L 21/301 (2006.01) ,C09J 7/20 (2018.01) ,C09J 201/00 (2006.01) ,H01L 21/304 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
301
to subdivide a semiconductor body into separate parts, e.g. making partitions
[IPC code unknown for C09J 7/20]
C CHEMISTRY; METALLURGY
09
DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
J
ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
201
Adhesives based on unspecified macromolecular compounds
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
304
Mechanical treatment, e.g. grinding, polishing, cutting
Applicants:
古河電気工業株式会社 FURUKAWA ELECTRIC CO., LTD. [JP/JP]; 東京都千代田区丸の内2丁目2番3号 2-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008322, JP
Inventors:
内山 具朗 UCHIYAMA, Tomoaki; JP
五島 裕介 GOTO, Yusuke; JP
Agent:
特許業務法人イイダアンドパートナーズ IIDA & PARTNERS; 東京都港区新橋3丁目1番10号 石井ビル3階 ISHII Bldg. 3F, 1-10, Shimbashi 3-chome, Minato-ku, Tokyo 1050004, JP
飯田 敏三 IIDA, Toshizo; JP
赤羽 修一 AKABA, Shuichi; JP
Priority Data:
2017-04643510.03.2017JP
Title (EN) ADHESIVE TAPE FOR SEMICONDUCTOR PROCESSING
(FR) BANDE ADHÉSIVE POUR TRAITEMENT DE SEMI-CONDUCTEURS
(JA) 半導体加工用粘着テープ
Abstract:
(EN) An adhesive tape for semiconductor processing, which is composed of a substrate and an adhesive layer that is provided on one surface of the substrate, and which is characterized in that: the substrate has a multilayer structure; at least one layer of the multilayer structure is a layer A that contains 80% by mass or more of a cyclic olefin polymer; and the multilayer structure comprises, in addition to the layer A, a layer B that contains a linear low-density polyethylene or a high-density polyethylene.
(FR) L'invention concerne une bande adhésive pour le traitement de semi-conducteurs, qui est composée d'un substrat et d'une couche adhésive qui est disposée sur une surface du substrat, et qui est caractérisée comme suit : le substrat a une structure multicouche ; au moins une couche de la structure multicouche est une couche A qui contient au moins 80 % en masse d'un polymère d'oléfine cyclique ; et la structure multicouche comprend, en plus de la couche A, une couche B qui contient un polyéthylène basse densité linéaire ou un polyéthylène haute densité.
(JA) 基材と、該基材の片面に設けられた粘着剤層とからなる粘着テープであって、前記基材が複層構造からなり、該複層構造の少なくとも1層が環状オレフィンポリマーを80質量%以上含有する層Aであって、該層Aとは別に、直鎖状低密度ポリエチレンまたは高密度ポリエチレンを含有する層Bを有することを特徴とする、半導体加工用粘着テープ。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)