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1. (WO2018163997) ACTIVE MATRIX SUBSTRATE AND METHOD FOR PRODUCING SAME
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Pub. No.: WO/2018/163997 International Application No.: PCT/JP2018/008062
Publication Date: 13.09.2018 International Filing Date: 02.03.2018
IPC:
H01L 29/786 (2006.01) ,G09F 9/30 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
30
in which the desired character or characters are formed by combining individual elements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
織田 明博 ODA Akihiro; --
武田 悠二郎 TAKEDA Yujiro; --
村重 正悟 MURASHIGE Shogo; --
松木薗 広志 MATSUKIZONO Hiroshi; --
Agent:
奥田 誠司 OKUDA Seiji; JP
Priority Data:
2017-04464309.03.2017JP
Title (EN) ACTIVE MATRIX SUBSTRATE AND METHOD FOR PRODUCING SAME
(FR) SUBSTRAT DE MATRICE ACTIVE ET PROCÉDÉ DE PRODUCTION DE CELUI-CI
(JA) アクティブマトリクス基板およびその製造方法
Abstract:
(EN) This active matrix substrate is provided with a substrate (1), a peripheral circuit which comprises a plurality of first TFTs 10, and a plurality of second TFTs (20). Each one of the first and second TFTs (10, 20) comprises: gate electrodes (3A, 3B); a gate insulating layer (5); oxide semiconductor layers (7A, 7B) which comprise channel regions (7Ac, 7Bc), and source contact regions (7As, 7Bs) and drain contact regions (7Ad, 7Bd) that are on both sides of the channel regions (7Ac, 7Bc); source electrodes (8A, 8B) which are in contact with the source contact regions; and drain electrodes (9A, 9B) which are in contact with the drain contact regions. The oxide semiconductor layers of the first TFTs and the second TFTs are formed from a same oxide semiconductor film; and the carrier concentration in the channel region (7Ac) of each first TFT is higher than the carrier concentration in the channel region (7Bc) of each second TFT.
(FR) Selon l'invention, un substrat de matrice active est pourvu d'un substrat (1), d'un circuit périphérique qui comprend une pluralité de premiers TFT (10), et d'une pluralité de deuxièmes TFT (20). Chacun des premiers et deuxièmes TFT (10, 20) comprend : des électrodes de grille (3A, 3B) ; une couche d'isolation de grille (5) ; des couches semi-conductrices d'oxyde (7A, 7B) qui comprennent des régions de canal (7Ac, 7Bc), et des régions de contact de source (7As, 7Bs) et des régions de contact de drain (7Ad, 7Bd) qui sont des deux côtés des régions de canal (7Ac, 7Bc) ; des électrodes de source (8A, 8B) qui sont en contact avec les régions de contact de source ; et des électrodes de drain (9A, 9B) qui sont en contact avec les régions de contact de drain. Les couches semi-conductrices d'oxyde des premiers TFT et des deuxièmes TFT sont formées à partir d'un même film d'oxyde semi-conducteur ; et la concentration en porteurs dans la région de canal (7Ac) de chaque premier TFT est supérieure à la concentration en porteurs dans la région de canal (7Bc) de chaque deuxième TFT.
(JA) アクティブマトリクス基板は、基板(1)と、複数の第1のTFT10を含む周辺回路と、複数の第2のTFT(20)とを備え、第1および第2のTFT(10、20)のそれぞれは、ゲート電極(3A、3B)と、ゲート絶縁層(5)と、チャネル領域(7Ac、7Bc)、およびその両側に位置するソースコンタクト領域(7As、7Bs)およびドレインコンタクト領域(7Ad、7Bd)を含む酸化物半導体層(7A、7B)と、ソースコンタクト領域に接するソース電極(8A、8B)と、ドレインコンタクト領域に接するドレイン電極(9A、9B)とを有し、第1のTFTおよび第2のTFTの酸化物半導体層は、同一の酸化物半導体膜から形成されており、第1のTFTのチャネル領域(7Ac)におけるキャリア濃度は、第2のTFTのチャネル領域(7Bc)におけるキャリア濃度よりも高い。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)