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1. (WO2018163599) SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR, AND SEMICONDUCTOR MODULE
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Pub. No.: WO/2018/163599 International Application No.: PCT/JP2018/000848
Publication Date: 13.09.2018 International Filing Date: 15.01.2018
IPC:
H01L 21/56 (2006.01) ,H01L 21/50 (2006.01) ,H01L 23/29 (2006.01) ,H01L 23/31 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
29
characterised by the material
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
31
characterised by the arrangement
Applicants:
三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 東京都千代田区丸の内二丁目7番3号 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors:
横山 吉典 YOKOYAMA, Yoshinori; JP
藤田 淳 FUJITA, Jun; JP
篠原 利彰 SHINOHARA, Toshiaki; JP
小林 浩 KOBAYASHI, Hiroshi; JP
Agent:
村上 加奈子 MURAKAMI, Kanako; JP
松井 重明 MATSUI, Jumei; JP
倉谷 泰孝 KURATANI, Yasutaka; JP
伊達 研郎 DATE, Kenro; JP
Priority Data:
2017-04389308.03.2017JP
Title (EN) SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR, AND SEMICONDUCTOR MODULE
(FR) DISPOSITIF À SEMICONDUCTEUR, SON PROCÉDÉ DE FABRICATION ET MODULE SEMICONDUCTEUR
(JA) 半導体装置、その製造方法および半導体モジュール
Abstract:
(EN) Obtained is a semiconductor device in which occurrence of chipping in a thin semiconductor element during conveyance is suppressed. The semiconductor device is provided with: a semiconductor element (1) having a front surface electrode (2) on the front surface side thereof and having a rear surface electrode (3) on the rear surface side thereof; a metallic member (4, 8) which has a thickness larger than the thickness of the semiconductor element (1) and which is formed on at least either the front surface electrode (2) or the rear surface electrode (3); and a resin member (5) from which a part of the front surface of the semiconductor element (1) is exposed and which surrounds the periphery of the metallic member (4, 8) by being in contact with a side surface of the metallic member (4, 8).
(FR) L'invention permet d'obtenir un dispositif à semiconducteur dans lequel l'apparition d'un écaillage dans un élément semiconducteur mince pendant le transport est supprimée. Le dispositif à semiconducteur comprend : un élément semiconducteur (1) ayant une électrode de surface avant (2) sur le côté de surface avant de celui-ci et ayant une électrode de surface arrière (3) sur son côté de surface arrière; un élément métallique (4, 8) qui a une épaisseur supérieure à l'épaisseur de l'élément semiconducteur (1) et qui est formé sur au moins l'électrode de surface avant (2) ou l'électrode de surface arrière (3); et un élément de résine (5) à partir duquel une partie de la surface avant de l'élément semiconducteur (1) est exposée et qui entoure la périphérie de l'élément métallique (4, 8) en étant en contact avec une surface latérale de l'élément métallique (4, 8).
(JA) 薄厚の半導体素子の搬送時における欠けの発生を抑制した半導体装置を得る。おもて面側に表面電極(2)を有し、裏面側に裏面電極(3)を有する薄厚の半導体素子(1)と、半導体素子(1)の厚み以上の厚みであり、表面電極(2)または裏面電極(3)の少なくとも一方に形成された金属部材(4,8)と、半導体素子(1)のおもて面の一部を露出し、金属部材(4,8)の側面と接して金属部材(4,8)の周囲を囲む樹脂部材(5)と、を備えた半導体装置。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)