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1. (WO2018163387) ANALYSIS DEVICE, ANALYSIS METHOD, AND ANALYSIS PROGRAM
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Pub. No.: WO/2018/163387 International Application No.: PCT/JP2017/009613
Publication Date: 13.09.2018 International Filing Date: 09.03.2017
IPC:
G06F 11/34 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
11
Error detection; Error correction; Monitoring
30
Monitoring
34
Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
Applicants:
三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 東京都千代田区丸の内二丁目７番３号 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors:
遠山　治 TOYAMA, Osamu; JP
外山　正勝 TOYAMA, Masakatsu; JP
Agent:
溝井国際特許業務法人 MIZOI INTERNATIONAL PATENT FIRM; 神奈川県鎌倉市大船二丁目１７番１０号３階 3rd floor, 17-10, Ofuna 2-chome, Kamakura-shi, Kanagawa 2470056, JP
Priority Data:
Title (EN) ANALYSIS DEVICE, ANALYSIS METHOD, AND ANALYSIS PROGRAM
(FR) DISPOSITIF D'ANALYSE, PROCÉDÉ D'ANALYSE ET PROGRAMME D'ANALYSE
(JA) 解析装置、解析方法及び解析プログラム
Abstract:
(EN) A program division unit (200) divides a program (100) including a plurality of instruction sequences into a plurality of basic blocks. An instruction execution delay time calculation unit (50) acquires a measurement section information (520) which indicates a measurement section designated as a range for calculation of an instruction execution delay time in the program (100), extracts a basic block included in the measurement section from the plurality of basic blocks, and calculates the instruction execution delay time of the extracted basic block.
(FR) L'invention concerne une unité de division de programme (200) qui divise un programme (100) comprenant une pluralité de séquences d'instructions en une pluralité de blocs de base. Une unité de calcul de temps de retard d'exécution d'instruction (50) acquiert des informations de section de mesure (520) qui indiquent une section de mesure désignée en tant que plage pour le calcul d'un temps de retard d'exécution d'instruction dans le programme (100), extrait un bloc de base compris dans la section de mesure à partir de la pluralité de blocs de base et calcule le temps de retard d'exécution d'instruction du bloc de base extrait.
(JA) プログラム分割部（２００）は、複数の命令列が含まれるプログラム（１００）を複数の基本ブロックに分割する。命令実行遅延時間算出部（５０）は、プログラム（１００）内で命令実行遅延時間の算出の対象の範囲として指定された測定区間が示される測定区間情報（５２０）を取得し、複数の基本ブロックから測定区間に含まれる基本ブロックを抽出し、抽出した基本ブロックの命令実行遅延時間を算出する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)