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1. (WO2018163286) SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/163286 International Application No.: PCT/JP2017/009007
Publication Date: 13.09.2018 International Filing Date: 07.03.2017
IPC:
H01L 29/78 (2006.01) ,H01L 29/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
Applicants:
三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 東京都千代田区丸の内二丁目7番3号 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors:
菅原 勝俊 SUGAWARA, Katsutoshi; JP
福井 裕 FUKUI, Yutaka; JP
足立 亘平 ADACHI, Kohei; JP
八田 英之 HATTA, Hideyuki; JP
Agent:
村上 加奈子 MURAKAMI, Kanako; JP
松井 重明 MATSUI, Jumei; JP
倉谷 泰孝 KURATANI, Yasutaka; JP
伊達 研郎 DATE, Kenro; JP
Priority Data:
Title (EN) SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE
(FR) DISPOSITIF À SEMICONDUCTEUR ET DISPOSITIF DE CONVERSION DE PUISSANCE
(JA) 半導体装置および電力変換装置
Abstract:
(EN) A silicon carbide semiconductor device (100) is provided with: a diffusion protection layer (9) that is provided below a gate insulating film (7) on the bottom surface of a gate trench (6); gate wiring (18), which is provided on an insulating film on the bottom surface of a terminal trench (16) positioned further toward the outer peripheral side than the gate trench (6), and which is electrically connected to a gate electrode (8); a gate pad (33) bonded to the gate wiring (18) in the terminal trench (16); a terminal protection layer (19) that is provided below the insulating film on the bottom surface of the terminal trench (16); and a source electrode (11) electrically connected to a source region (5), the diffusion protection layer (9), and the terminal protection layer (19). At a first extending section (9a) extending toward the terminal protection layer (19), the diffusion protection layer (9) is separated from the terminal protection layer (19). Application of an excessive electric field to the gate insulating film provided on the bottom surface of the gate trench is suppressed.
(FR) L'invention concerne un dispositif à semiconducteur au carbure de silicium (100) comprenant : une couche de protection contre la diffusion (9) qui est disposée au-dessous d'un film d'isolation de grille (7) sur la surface inférieure d'une tranchée de grille (6); un câblage de grille (18), qui est disposé sur un film d'isolation sur la surface inférieure d'une tranchée de borne (16) positionnée davantage vers le côté périphérique externe que la tranchée de grille (6), et qui est électriquement connecté à une électrode de grille (8); une pastille de grille (33) liée au câblage de grille (18) dans la tranchée de borne (16); une couche de protection de borne (19) qui est disposée au-dessous du film d'isolation sur la surface inférieure de la tranchée de borne (16); et une électrode de source (11) connectée électriquement à une région de source (5), à la couche de protection contre la diffusion (9), et à la couche de protection de borne (19). Au niveau d'une première section d'extension (9a) s'étendant vers la couche de protection de borne (19), la couche de protection contre la diffusion (9) est séparée de la couche de protection de borne (19). L'application d'un champ électrique excessif au film d'isolation de grille disposé sur la surface inférieure de la tranchée de grille est supprimée.
(JA) 炭化珪素半導体装置(100)は、ゲートトレンチ(6)の底面のゲート絶縁膜(7)の下方に設けられた拡散保護層(9)と、ゲートトレンチ(6)よりも外周側に位置する終端トレンチ(16)の底面の絶縁膜上に設けられゲート電極(8)に電気的に接続されたゲート配線(18)と、終端トレンチ(16)内でゲート配線(18)に接合されたゲートパッド(33)と、終端トレンチ(16)の底面の絶縁膜の下方に設けられた終端保護層(19)と、ソース領域(5)、拡散保護層(9)、および終端保護層(19)に電気的に接続されたソース電極(11)と、を備え、拡散保護層(9)は、終端保護層(19)に向かって延伸した第1の延伸部(9a)で終端保護層(19)と離隔する。ゲートトレンチの底面に設けられたゲート絶縁膜に過大な電界が印加されるのを抑制する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)