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1. (WO2018161865) STAIRCASE ETCH CONTROL IN FORMING THREE-DIMENSIONAL MEMORY DEVICE

Pub. No.:    WO/2018/161865    International Application No.:    PCT/CN2018/077931
Publication Date: Fri Sep 14 01:59:59 CEST 2018 International Filing Date: Sat Mar 03 00:59:59 CET 2018
IPC: H01L 27/11551
H01L 27/11578
H01L 23/544
H01L 21/68
Applicants: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Inventors: LU, Zhenyu
SONG, Lidong
LI, Yongna
PAN, Feng
DAI, Xiaowang
LIU, Dan
YANG, Steve, Weiyi
YANG, Simon, Shi-Ning
Title: STAIRCASE ETCH CONTROL IN FORMING THREE-DIMENSIONAL MEMORY DEVICE
Abstract:
Three-dimensional (3D) memory devices and methods for controlling a photoresist (PR) trimming rate in the formation of the 3D memory devices are disclosed. A method includes forming a dielectric stack over a substrate, measuring a first distance between the first trimming mark and the PR layer along a first direction, and trimming the PR layer along the first direction. The method also includes etching the dielectric stack using the trimmed PR layer as an etch mask to form a staircase, forming a second trimming mark using the first trimming mark as an etch mask, measuring a second distance between the second trimming mark and the trimmed PR layer, comparing the first distance with the second distance to determine a difference between an actual PR trimming rate and an estimated PR trimming rate, and adjusting PR trimming parameters based on the difference.