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1. (WO2018161841) STRUCTURE AND METHOD FOR TESTING THREE-DIMENSIONAL MEMORY DEVICE

Pub. No.:    WO/2018/161841    International Application No.:    PCT/CN2018/077754
Publication Date: Fri Sep 14 01:59:59 CEST 2018 International Filing Date: Fri Mar 02 00:59:59 CET 2018
IPC: H01L 27/11548
H01L 27/11551
H01L 27/11575
H01L 27/11578
H01L 21/66
Applicants: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Inventors: KIM, Jong Jun
PAN, Feng
LEE, Jong Seuk
LU, Zhenyu
LI, Yongna
SONG, Lidong
KIM, Youn Cheul
YANG, Steve Weiyi
YANG, Simon Shi-Ning
Title: STRUCTURE AND METHOD FOR TESTING THREE-DIMENSIONAL MEMORY DEVICE
Abstract:
Structures and methods for testing three-dimensional (3D) memory devices (100) are disclosed. A 3D memory device (100) includes a memory array structure (102), a peripheral device structure (104), and an interconnect layer (106) in contact with a front side of the memory array structure (102) and a front side of the peripheral device structure (104), and a conductive pad (108) at a back side of the memory array structure (102) and that overlaps the memory array structure (102). The memory array structure (102) includes a memory array stack (109), a through array contact (TAC) (110) extending vertically through at least part of the memory array stack (109), and a memory array contact (112). The peripheral device structure (104) includes a test circuit (126). The interconnect layer (106) includes an interconnect structure (116, 124). The conductive pad (108), the TAC (110), the interconnect structure (116, 124), and at least one of the test circuit (126) and the memory array contact (112) are electrically connected.