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1. (WO2018161561) SHIFT REGISTER, DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT AND DISPLAY DEVICE
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Pub. No.: WO/2018/161561 International Application No.: PCT/CN2017/105496
Publication Date: 13.09.2018 International Filing Date: 10.10.2017
IPC:
G09G 3/20 (2006.01) ,G11C 19/28 (2006.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
19
Digital stores in which the information is moved stepwise, e.g. shift registers
28
using semiconductor elements
Applicants:
BOE TECHNOLOGY GROUP CO. , LTD. [CN/CN]; No. 10 Jiuxianqiao Rd. , Chaoyang District Beijing 100015, CN
HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO. , LTD. [CN/CN]; Xinzhan Industrial Park Hefei, Anhui 230012, CN
Inventors:
ZHANG, Miao; CN
CHEN, Mo; CN
SUN, Jing; CN
FU, Wuxia; CN
Agent:
TEE&HOWE INTELLECTUAL PROPERTY ATTORNEYS; CHEN, Yuan 10th Floor, Tower D, Minsheng Financial Center 28 Jianguomennei Avenue, Dongcheng District Beijing 100005, CN
Priority Data:
201710137323.909.03.2017CN
Title (EN) SHIFT REGISTER, DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT AND DISPLAY DEVICE
(FR) REGISTRE À DÉCALAGE, SON PROCÉDÉ DE COMMANDE, CIRCUIT DE COMMANDE DE GRILLE ET DISPOSITIF D’AFFICHAGE
Abstract:
(EN) A shift register (200) includes a first input circuit (10), a second input circuit (20), and a pull-up transistor (M3). The first input circuit (10) is coupled to a first input terminal (IN_1) and a first pull-up node (PU_1), and configured to electrically connect the first input terminal (IN_1) to the first pull-up node (PU_1) when the first input terminal (IN_1) receives an active signal. The second input circuit (20) is coupled to a second input terminal (IN_2) and a second pull-up node (PU_2), and configured to electrically connect the second input terminal (IN_2) to the second pull-up node (PU_2) when the second input terminal (IN_2) receives an active signal. The pull-up transistor (M3) includes a first gate electrode coupled to the first pull-up node (PU_1) and a second gate electrode coupled to the second pull-up node (PU_2).
(FR) Selon l’invention, un registre à décalage (200) comporte un premier circuit d’entrée (10), un second circuit d’entrée (20) et un transistor de tirage vers le haut (M3). Le premier circuit d’entrée (10) est couplé à une première borne d’entrée (IN_1) et à un premier nœud de tirage vers le haut (PU_1), et est configuré pour connecter électriquement la première borne d’entrée (IN_1) au premier nœud de tirage vers le haut (PU_1) lorsque la première borne d’entrée (IN_1) reçoit un signal actif. Le second circuit d’entrée (20) est couplé à une seconde borne d’entrée (IN_2) et à un second nœud de tirage vers le haut (PU_2), et est configuré pour connecter électriquement la seconde borne d’entrée (IN_2) au second nœud de tirage vers le haut (PU_2) lorsque la seconde borne d’entrée (IN_2) reçoit un signal actif. Le transistor de tirage vers le haut (M3) comporte une première électrode de grille couplée au premier nœud de tirage vers le haut (PU_1) et une seconde électrode de grille couplée au second nœud de tirage vers le haut (PU_2).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)