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1. (WO2018161431) MEMORY-BASED CIRCUIT BOARD
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Pub. No.: WO/2018/161431 International Application No.: PCT/CN2017/083834
Publication Date: 13.09.2018 International Filing Date: 10.05.2017
IPC:
G06F 13/40 (2006.01) ,G06F 13/42 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38
Information transfer, e.g. on bus
40
Bus structure
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38
Information transfer, e.g. on bus
42
Bus transfer protocol, e.g. handshake; Synchronisation
Applicants: SZ DJI TECHNOLOGY CO., LTD.[CN/CN]; 6F, HKUST SZ IER Bldg. No. 9 Yuexing 1st Rd. Hi-Tech Park (South), Nanshan District Shenzhen, Guangdong 518057, CN
Inventors: YE, Yongyun; CN
Agent: SHENZHEN SCIENBIZIP INTELLECTUAL PROPERTY AGENCY CO., LTD.; 9F, Rongqun Building No. 83 Longguan East Rd., Longhua new Dist. Shenzhen, Guangdong 518109, CN
Priority Data:
201720232640.410.03.2017CN
Title (EN) MEMORY-BASED CIRCUIT BOARD
(FR) CARTE DE CIRCUIT IMPRIMÉ COMPRENANT UNE MÉMOIRE
(ZH) 基于存储器的电路板
Abstract:
(EN) A memory-based circuit board (1) is provided. A memory (2) is disposed on the circuit board (1). A processor (3) configured to control the memory (2) is further disposed on the circuit board (1). The memory (2) and the processor (3) both comprise at least two sets of signal lines. A line set identifier of each set of the signal lines of the memory (2) corresponds to a line set identifier of each set of the signal lines of the processor (3). Signal lines of the memory (2) and the processor (3) have no cross connection on the same layer of the circuit board. Line set identifiers of the connected memory (2) and the processor (3) do not correspond to each other. Thus, by exchanging signals between the memory (2) and the processor (3) using signal line sets as units, the arrangement of the signal lines of the memory (2) and the processor (3) is facilitated, and it is ensured that the signal lines of the two do not cross each other, such that communication quality of signals is ensured.
(FR) L’invention concerne une carte de circuit imprimé comprenant une mémoire. Une mémoire (2) est disposée sur la carte de circuit imprimé (1). L'invention concerne également un processeur (3) configuré pour commander la mémoire (2) qui est en outre disposé sur la carte de circuit imprimé (1). La mémoire (2) et le processeur (3) comprennent tous deux au moins deux ensembles de lignes de signaux. Un identifiant d'ensemble de lignes de chaque ensemble des lignes de signaux de la mémoire (2) correspond à un identifiant d'ensemble de lignes de chaque ensemble des lignes de signaux du processeur (3). Des lignes de signaux de la mémoire (2) et du processeur (3) n'ont pas de connexion croisée sur la même couche de la carte de circuit imprimé. Des identifiants d'ensemble de lignes de la mémoire connectée (2) et du processeur (3) ne correspondent pas les uns aux autres. Ainsi, en échangeant des signaux entre la mémoire (2) et le processeur (3) à l'aide d'ensembles de lignes de signaux en tant qu'unités, l'agencement des lignes de signaux de la mémoire (2) et le processeur (3) est facilité, et il est garanti que les lignes de signaux des deux ne se croisent pas, de telle sorte que la qualité de communication des signaux est assurée.
(ZH) 一种基于存储器的电路板(1),在电路板(1)上设置有存储器(2),还设置有用于控制存储器(2)的处理器(3);存储器(2)和处理器(3)均包含有至少两组信号线;其中,存储器(2)上每组信号线的线组标识与处理器(3)上每组信号线的线组标识相对应;存储器(2)的信号线和处理器(3)的信号线,在同层电路板上无交叉连接;其中,相连接的存储器(2)的线组标识与处理器(3)的线组标识为非对应的线组标识。从而通过以信号线组为单位交换存储器(2)和处理器(3)之间的信号,方便存储器(2)和处理器(3)间的信号线的走线,保证两者间的信号线没有交叉,进而保证信号间的通信质量。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)