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1. (WO2018160785) PINNING THE CONVERSION POINT BELOW THE EPILAYER INTERFACE FOR SiC POWER DEVICE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/160785 International Application No.: PCT/US2018/020362
Publication Date: 07.09.2018 International Filing Date: 01.03.2018
IPC:
C30B 25/18 (2006.01) ,C30B 29/36 (2006.01) ,C30B 25/22 (2006.01) ,H01L 21/306 (2006.01) ,H01L 21/02 (2006.01) ,H01L 21/3065 (2006.01)
C CHEMISTRY; METALLURGY
30
CRYSTAL GROWTH
B
SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
25
Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour deposition growth
02
Epitaxial-layer growth
18
characterised by the substrate
C CHEMISTRY; METALLURGY
30
CRYSTAL GROWTH
B
SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
29
Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
10
Inorganic compounds or compositions
36
Carbides
C CHEMISTRY; METALLURGY
30
CRYSTAL GROWTH
B
SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
25
Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour deposition growth
02
Epitaxial-layer growth
22
Sandwich processes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
3065
Plasma etching; Reactive-ion etching
Applicants: UNIVERSITY OF SOUTH CAROLINA[US/US]; OSBORNE ADMINISTRATION BUILDING, SUITE 109 COLUMBIA, South Carolina 29208, US
Inventors: BALACHANDRAN, Anusha; US
CHANDRASHEKHAR, Mvs; US
SUDARSHAN, Tangali S.; US
Agent: MANGELSEN, Christina, L.; US
BATAVIA, Neil, M.; US
Priority Data:
62/465,92502.03.2017US
Title (EN) PINNING THE CONVERSION POINT BELOW THE EPILAYER INTERFACE FOR SiC POWER DEVICE
(FR) ANCRAGE DU POINT DE CONVERSION EN DESSOUS DE L'INTERFACE DE COUCHE ÉPITAXIALE POUR UN DISPOSITIF DE PUISSANCE SIC
Abstract:
(EN) Methods are provided for growing basal plane dislocation (BPD)-free SiC device-ready epilayers, particularly suitable for 4H-SiC devices. The devices are formed via a substantially 100% conversion of BPDs to threading edge dislocations (TEDs) while pinning the conversion point below the epilayer interface. Methods include the formation of a recombination layer on a previously formed and etched buffer layer. Devices allow for improved reliability and efficiency of high voltage switches used in the day-to-day applications such as inverters, uninterrupted power supplies, and other high power handling devices employed in hybrid electric vehicles, aircraft electronic systems, etc. by enabling the manufacture of smaller, lighter, and more efficient, high power SiC devices in a cost effective, reliable platform.
(FR) L'invention concerne des procédés de croissance de couches épitaxiales prêtes à l'emploi sur dispositifs SiC et exemptes de dislocations dans le plan basal (BPD), convenant en particulier à des dispositifs 4H-SiC. Les dispositifs sont formés par l'intermédiaire d'une conversion sensiblement à 100 % de dislocations BPD en dislocations en coin (TEDs) tout en ancrant le point de conversion en dessous de l'interface de couche épitaxiale. Des procédés comprennent la formation d'une couche de recombinaison sur une couche tampon préalablement formée et gravée. Les dispositifs permettent d'améliorer la fiabilité et l'efficacité de commutateurs à haute tension utilisés dans des applications courantes telles que des onduleurs, des alimentations sans coupure et d'autres dispositifs de gestion de grande puissance employés dans des véhicules électriques hybrides, des systèmes électroniques d'aéronef, etc. en permettant la fabrication de dispositifs SiC de grande puissance plus petits, plus légers et plus efficaces, dans une plate-forme fiable et rentable.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)