Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2018160569) FEEDFORWARD PHASE NOISE COMPENSATION
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/160569 International Application No.: PCT/US2018/019963
Publication Date: 07.09.2018 International Filing Date: 27.02.2018
IPC:
H04L 27/18 (2006.01) ,H03M 1/50 (2006.01)
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
27
Modulated-carrier systems
18
Phase-modulated carrier systems, i.e. using phase-shift keying
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
1
Analogue/digital conversion; Digital/analogue conversion
12
Analogue/digital converters
50
with intermediate conversion to time interval
Applicants:
ANALOG DEVICES GLOBAL UNLIMITED COMPANY; 3rd Floor, Par La Ville Place 14 Par La Ville Road Hamilton, BM
Inventors:
THIJSSEN, Bartholomeus, Jacobus; BM
KLUMPERINK, Eric, Antonius, Maria; BM
NAUTA, Bram; BM
QUINLAN, Philip, Eugene; BM
Priority Data:
62/465,71701.03.2017US
Title (EN) FEEDFORWARD PHASE NOISE COMPENSATION
(FR) COMPENSATION DE BRUIT DE PHASE PRÉDICTIVE
Abstract:
(EN) Clock systems with phase noise compensation are provided herein. In certain implementations, a clock system includes a phase noise detector for detecting a phase noise of a clock signal, and an adjustable delay circuit for generating an adjusted clock signal based on delaying the clock signal with a controllable delay. Additionally, the phase noise detector generates an error signal indicated the phase noise of the clock signal, and controls the delay of the adjustable delay circuit with the error signal over time to thereby compensate the clock signal for phase noise. Thus, the adjusted clock signal has reduced phase noise compared to the clock signal.
(FR) L'invention concerne des systèmes d'horloge à compensation de bruit de phase. Dans certains modes de réalisation, un système d'horloge comprend un détecteur de bruit de phase, qui permet de détecter un bruit de phase d'un signal d'horloge, et un circuit de retard ajustable, qui permet de générer un signal d'horloge ajusté sur la base du retard du signal d'horloge à l'aide d'un retard pouvant être commandé. De plus, le détecteur de bruit de phase génère un signal d'erreur, indiqué par le bruit de phase du signal d'horloge, et commande le retard du circuit à retard ajustable à l'aide du signal d'erreur au fil du temps afin de compenser le signal d'horloge concernant le bruit de phase. Ainsi, le signal d'horloge ajusté présente un bruit de phase réduit par rapport au signal d'horloge.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)