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1. (WO2018160330) NEURAL NETWORK PROCESSING WITH CHAINED INSTRUCTIONS
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Pub. No.: WO/2018/160330 International Application No.: PCT/US2018/017309
Publication Date: 07.09.2018 International Filing Date: 08.02.2018
IPC:
G06N 3/04 (2006.01) ,G06F 9/48 (2006.01) ,G06N 3/063 (2006.01) ,H03K 19/177 (2006.01) ,G06F 9/30 (2018.01) ,G06F 9/38 (2018.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
N
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3
Computer systems based on biological models
02
using neural network models
04
Architecture, e.g. interconnection topology
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
46
Multiprogramming arrangements
48
Programme initiating; Programme switching, e.g. by interrupt
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
N
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3
Computer systems based on biological models
02
using neural network models
06
Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
063
using electronic means
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
19
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02
using specified components
173
using elementary logic circuits as components
177
arranged in matrix form
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
38
Concurrent instruction execution, e.g. pipeline, look ahead
Applicants:
MICROSOFT TECHNOLOGY LICENSING, LLC [US/US]; One Microsoft Way Redmond, Washington 98052-6399, US
Inventors:
FOWERS, Jeremy; US
CHUNG, Eric S.; US
BURGER, Douglas C.; US
Agent:
MINHAS, Sandip S.; US
CHEN, Wei-Chen Nicholas; US
DRAKOS, Katherine J.; US
HINOJOSA, Brianna L.; US
HOLMES, Danielle J.; US
SWAIN, Cassandra T.; US
WONG, Thomas S.; US
CHOI, Daniel; US
HWANG, William C.; US
WIGHT, Stephen A.; US
CHATTERJEE, Aaron C.; US
Priority Data:
15/637,49529.06.2017US
62/465,06328.02.2017US
Title (EN) NEURAL NETWORK PROCESSING WITH CHAINED INSTRUCTIONS
(FR) TRAITEMENT DE RÉSEAU NEURONAL AVEC DES INSTRUCTIONS EN CHAÎNE
Abstract:
(EN) Hardware and methods for neural network processing are provided. A method in a hardware node including a pipeline having a matrix vector unit (MVU), a first multifunction unit connected to receive an input from the matrix vector unit, a second multifunction unit connected to receive an output from the first multifunction unit, and a third multifunction unit connected to receive an output from the second multifunction unit is provided. The method includes performing using the MVU a first type of instruction that can only be performed by the MVU to generate a first result. The method further includes performing a second type of instruction that can only be performed by one of the multifunction units and generating a second result and without storing the any of the two results in a global register, passing the second result to the second multifunction and the third multifunction unit.
(FR) L'invention concerne un matériel et des procédés de traitement de réseau neuronal. Un procédé dans un nœud matériel comprend un conduit ayant une unité de vecteur de matrice (MVU), une première unité multifonction connectée pour recevoir une entrée provenant de l'unité de vecteur de matrice, une deuxième unité multifonction connectée pour recevoir une sortie de la première unité multifonction, et une troisième unité multifonction connectée pour recevoir une sortie de la deuxième unité multifonction. Le procédé comprend l'exécution, à l'aide de la MVU, d'un premier type d'instruction qui peut uniquement être effectué par la MVU pour générer un premier résultat. Le procédé comprend en outre la réalisation d'un second type d'instruction qui peut uniquement être effectué par l'une des unités multifonction et la génération d'un second résultat et sans stocker l'un quelconque des deux résultats dans un registre global, faire passer le second résultat à la deuxième unité multifonction et à la troisième unité multifonction.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)