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1. (WO2018160309) MEMORY CIRCUIT WITH WRITE-BYPASS PORTION

Pub. No.:    WO/2018/160309    International Application No.:    PCT/US2018/016003
Publication Date: Sat Sep 08 01:59:59 CEST 2018 International Filing Date: Wed Jan 31 00:59:59 CET 2018
IPC: G06F 12/0893
G11C 11/44
G11C 8/14
G11C 8/08
H01L 39/22
Applicants: NORTHROP GRUMMAN SYSTEMS CORPORATION
Inventors: KONIGSBURG, Brian
TSCHIRHART, Paul, Kenton
Title: MEMORY CIRCUIT WITH WRITE-BYPASS PORTION
Abstract:
One example includes a memory circuit. The memory circuit includes a memory array in which contiguous rows of the memory array are organized as a write-bypass portion that comprises a first portion of the rows and a main memory portion that includes a remaining portion of the rows. A given data word is stored in each of a row in the write-bypass portion and another row in the main memory portion during a data write operation in response to word-write signals and bit- write signals associated with each of the respective plurality of contiguous columns. The circuit also includes a control logic configured to store data associated with storage locations of the given data word in each of the row in the write-bypass portion and the other row in the main memory portion to facilitate access of the given data word during a data read operation.