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1. (WO2018159978) MICROCIRCUIT FORMING METHOD AND ETCHING FLUID COMPOSITION
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Pub. No.: WO/2018/159978 International Application No.: PCT/KR2018/002378
Publication Date: 07.09.2018 International Filing Date: 27.02.2018
IPC:
H05K 3/10 (2006.01) ,H05K 3/06 (2006.01) ,H05K 1/09 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
10
in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
02
in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
06
the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
09
Use of materials for the metallic pattern
Applicants:
(주)잉크테크 INKTEC CO., LTD. [KR/KR]; 경기도 안산시 단원구 능안로 108 (신길동) (Singil-dong) 108, Neungan-ro, Danwon-gu Ansan-si Gyeonggi-do 15426, KR
Inventors:
김수한 KIM, Su Han; KR
정광춘 CHUNG, Kwang-Choon; KR
문정윤 MOON, Jung Yoon; KR
하성인 HA, Sung In; KR
문병웅 MOON, Byung Woong; KR
Agent:
조영현 CHO, Young Hyun; KR
Priority Data:
10-2017-002794703.03.2017KR
Title (EN) MICROCIRCUIT FORMING METHOD AND ETCHING FLUID COMPOSITION
(FR) PROCÉDÉ DE FORMATION DE MICROCIRCUIT ET COMPOSITION DE FLUIDE DE GRAVURE
(KO) 미세 회로 형성방법 및 에칭액 조성물
Abstract:
(EN) The present invention relates to a microcircuit forming method. The microcircuit forming method according to the present invention comprises: a seed layer forming step for forming a high-reflectivity seed layer on a substrate material by using a conductive material; a pattern layer forming step for forming a pattern layer on the seed layer, the pattern layer having a pattern hole arranged thereon to allow the seed layer to be selectively exposed therethrough; a plating step for filling the pattern hole with a conductive material; a pattern layer removing step for removing the pattern layer; and a seed layer pattering step for removing a part of the seed layer which does not overlap the conductive material in the plating step, wherein the high-reflectivity seed layer has a specular reflection property.
(FR) La présente invention concerne un procédé de formation de microcircuit. Le procédé de formation de microcircuit selon la présente invention comprend : une étape de formation de couche de germe pour former une couche de germe à réflectivité élevée sur un matériau de substrat en utilisant un matériau conducteur ; une étape de formation de couche de motif pour former une couche de motif sur la couche de germe, la couche de motif ayant un trou de motif disposé sur celle-ci pour permettre à la couche de germe d'être exposée sélectivement à travers celui-ci ; une étape de placage pour remplir le trou de motif avec un matériau conducteur ; une étape d'enlèvement de couche de motif pour retirer la couche de motif ; et une étape de formation de motif sur la couche de germe pour retirer une partie de la couche de germe qui ne chevauche pas le matériau conducteur dans l'étape de placage, la couche de germe à haute réflectivité ayant une propriété de réflexion spéculaire.
(KO) 본 발명은 미세 회로 형성방법에 관한 것으로서, 본 발명에 따른 미세 회로 형성방법은 기판소재 상에 전도성물질로 고반사율 시드(Seed)층을 형성하는 시드층 형성단계;와, 상기 시드층 상에 상기 시드층이 선택적으로 노출되도록 패턴홈이 마련된 패턴층을 형성하는 패턴층 형성단계;와, 전도성물질로 상기 패턴홈을 충진하는 도금단계;와, 상기 패턴층을 제거하는 패턴층 제거단계; 및 상기 도금단계의 전도성물질과 중첩되지 않은 부분의 시드층을 제거하는 시드층 패터닝단계;를 포함하며, 상기 고반사율 시드층은 정반사 특성을 갖는 것을 특징으로 한다.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)