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1. (WO2018159309) SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
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Pub. No.: WO/2018/159309 International Application No.: PCT/JP2018/005301
Publication Date: 07.09.2018 International Filing Date: 15.02.2018
IPC:
H01L 21/52 (2006.01) ,H01L 25/065 (2006.01) ,H01L 25/07 (2006.01) ,H01L 25/18 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
52
Mounting semiconductor bodies in containers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
Applicants:
株式会社デンソー DENSO CORPORATION [JP/JP]; 愛知県刈谷市昭和町1丁目1番地 1-1, Showa-cho, Kariya-city, Aichi 4488661, JP
Inventors:
馬渡 和明 MAWATARI Kazuaki; JP
Agent:
特許業務法人ゆうあい特許事務所 YOU-I PATENT FIRM; 愛知県名古屋市中区錦一丁目6番5号 名古屋錦シティビル4階 Nagoya Nishiki City Bldg. 4F 1-6-5, Nishiki, Naka-ku, Nagoya-shi, Aichi 4600003, JP
Priority Data:
2017-04067003.03.2017JP
Title (EN) SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体装置およびその製造方法
Abstract:
(EN) This semiconductor devices provided with a substrate (1), a semiconductor chip (2) which is arranged on the front surface of the substrate (1), an adhesive (3) which fixes the back surface of the semiconductor chip (2) to the front surface of the substrate (1), and spacers (4) which regulate the distance between the substrate (1) and the semiconductor chip (2), wherein the spacers (4) are bonded to the front surface of the substrate (1) and the back surface of the semiconductor chip (2), and, in the in-plane direction on the back surface of the semiconductor chip (2), the spacers (4) are positioned at the vertices of a polygon that surrounds the center of gravity of the semiconductor chip (2).
(FR) La présente invention concerne des dispositifs à semi-conducteur qui sont pourvus d'un substrat (1), d'une puce semi-conductrice (2) disposée sur la surface avant du substrat (1), d'un adhésif (3) qui fixe la surface arrière de la puce semi-conductrice (2) à la surface avant du substrat (1) et d'éléments d'espacement (4) qui régulent la distance entre le substrat (1) et la puce semi-conductrice (2), les éléments d'espacement (4) étant liées à la surface avant du substrat (1) et à la surface arrière de la puce semi-conductrice (2), et positionnées, dans la direction dans le plan sur la surface arrière de la puce semi-conductrice (2), au niveau des sommets d'un polygone qui entoure le centre de gravité de la puce semi-conductrice (2).
(JA) 半導体装置は、基板(1)と、基板(1)の表面側に配置された半導体チップ(2)と、半導体チップ(2)の裏面を基板(1)の表面に固定する接着剤(3)と、基板(1)と半導体チップ(2)との距離を規定する複数のスペーサ(4)と、を備え、スペーサ(4)は、基板(1)の表面、または、半導体チップ(2)の裏面に接合され、半導体チップ(2)の裏面の面内方向において、半導体チップ(2)の重心を囲む多角形の各頂点に位置している。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)