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1. (WO2018159186) SEMICONDUCTOR DEVICE, LAMINATE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND LAMINATE MANUFACTURING METHOD
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Pub. No.: WO/2018/159186 International Application No.: PCT/JP2018/002855
Publication Date: 07.09.2018 International Filing Date: 30.01.2018
IPC:
H01L 21/60 (2006.01) ,H01L 25/065 (2006.01) ,H01L 25/07 (2006.01) ,H01L 25/18 (2006.01) ,H01R 11/01 (2006.01) ,H05K 3/32 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
R
ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
11
Individual connecting elements providing two or more spaced connecting locations for conductive members which are, or may be, thereby interconnected, e.g. end pieces for wires or cables supported by the wire or cable and having means for facilitating electrical connection to some other wire, terminal, or conductive member, blocks of binding posts
01
characterised by the form or arrangement of the conductive interconnection between their connecting locations
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
30
Assembling printed circuits with electric components, e.g. with resistor
32
electrically connecting electric components or wires to printed circuits
Applicants: FUJIFILM CORPORATION[JP/JP]; 26-30, Nishiazabu 2-chome, Minato-ku, Tokyo 1068620, JP
Inventors: YAMASHITA Kosuke; JP
Agent: NAKASHIMA Junko; JP
YONEKURA Junzo; JP
MURAKAMI Yasunori; JP
Priority Data:
2017-03724228.02.2017JP
Title (EN) SEMICONDUCTOR DEVICE, LAMINATE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND LAMINATE MANUFACTURING METHOD
(FR) DISPOSITIF À SEMI-CONDUCTEUR, STRATIFIÉ, PROCÉDÉ DE FABRICATION DE DISPOSITIF À SEMI-CONDUCTEUR ET PROCÉDÉ DE FABRICATION DE STRATIFIÉ
(JA) 半導体デバイス、積層体ならびに半導体デバイスの製造方法および積層体の製造方法
Abstract:
(EN) Provided are: a semiconductor device and a laminate having good electrical insulation properties, high operational reliability, and high conductivity even when an anisotropic conductive member has a crack; and a manufacturing method of the semiconductor device, and a manufacturing method of the laminate. The semiconductor device has: an anisotropic conductive member that has an insulating base material, and a plurality of conductive paths which are provided so as to penetrate the insulating base material in the thickness direction and to be electrically insulated from one another; and at least two connection members each provided with electrodes. At least one of said at least two connection members is a semiconductor element. The anisotropic conductive member has an electrode connection region connected to the electrodes, and an electrode non-connection region not connected to the electrodes. Said at least two connection members are electrically connected by means of the anisotropic conductive member. The average value of a total crack length per unit area is 1 µm/mm2 or lower in the electrode connection region.
(FR) L'invention concerne : un dispositif à semi-conducteur et un stratifié ayant de bonnes propriétés d'isolation électrique, une fiabilité de fonctionnement élevée et une conductivité élevée même lorsqu'un élément conducteur anisotrope présente une fissure ; et un procédé de fabrication du dispositif à semi-conducteur, et un procédé de fabrication du stratifié. Le dispositif à semi-conducteur comprend : un élément conducteur anisotrope qui comporte un matériau de base isolant, et une pluralité de chemins conducteurs qui sont disposés de façon à pénétrer dans le matériau de base isolant dans le sens de l'épaisseur et à être isolés électriquement les uns des autres ; et au moins deux éléments de connexion pourvus chacun d'électrodes. Au moins l'un desdits deux éléments de connexion est un élément semi-conducteur. L'élément conducteur anisotrope comporte une région de connexion d'électrode connectée aux électrodes, et une région de non-connexion d'électrode qui n'est pas connectée aux électrodes. Lesdits deux éléments de connexion sont connectés électriquement au moyen de l'élément conducteur anisotrope. La valeur moyenne d'une longueur de fissure totale par unité de surface est inférieure ou égale à 1 µm/mm2 dans la région de connexion d'électrode.
(JA) 異方導電性部材にクラックがあっても導通が良好であり、かつ電気絶縁性が良好であり動作信頼性が高い半導体デバイス、積層体ならびに半導体デバイスの製造方法および積層体の製造方法を提供する。半導体デバイスは、絶縁性基材、および絶縁性基材の厚み方向に貫通し、互いに電気的に絶縁された状態で設けられた、複数の導通路を有する異方導電性部材と、それぞれ電極を備える少なくとも2つの被接続部材とを有する。少なくとも2つの被接続部材のうち、少なくとも1つは半導体素子である。異方導電性部材は電極と接続されている電極接続領域と、電極と接続されていない電極非接続領域を有する。異方導電性部材により少なくとも2つの被接続部材は電気的に接続されている。電極接続領域において単位面積当りの合計クラック長の平均値が1μm/mm以下である。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)