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1. (WO2018159185) SWITCH DEVICE
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Pub. No.: WO/2018/159185 International Application No.: PCT/JP2018/002821
Publication Date: 07.09.2018 International Filing Date: 30.01.2018
IPC:
H01L 21/822 (2006.01) ,H01L 21/82 (2006.01) ,H01L 27/04 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
Applicants:
株式会社村田製作所 MURATA MANUFACTURING CO., LTD. [JP/JP]; 京都府長岡京市東神足1丁目10番1号 10-1, Higashikotari 1-chome, Nagaokakyo-shi, Kyoto 6178555, JP
Inventors:
関 健太 SEKI, Kenta; JP
Agent:
稲葉 良幸 INABA, Yoshiyuki; JP
大貫 敏史 ONUKI, Toshifumi; JP
Priority Data:
2017-03696028.02.2017JP
Title (EN) SWITCH DEVICE
(FR) DISPOSITIF DE COMMUTATION
(JA) スイッチ装置
Abstract:
(EN) Provided is a switch device in which an increase in insertion loss is suppressed. This switch device is provided with: first to third layers laminated in sequence on the main surface of a substrate; a plurality of input terminals; a plurality of output terminals; a plurality of switch circuits; and a plurality of paths each electrically connecting one of the plurality of input terminals and one of the plurality output terminals through one of the plurality of switch circuits, wherein the plurality of paths include first and second paths crossing each other in a plane view of the main surface of the substrate, and in a crossing area in which the first and second paths cross each other, the first path is formed in the first layer, the second path is formed in the third layer, and none of the plurality of paths is formed in the second layer.
(FR) L'invention concerne un dispositif de commutation dans lequel une augmentation de la perte d'insertion est supprimée. Ce dispositif de commutation comprend : des première à troisième couches stratifiées en séquence sur la surface principale d'un substrat; une pluralité de bornes d'entrée; une pluralité de bornes de sortie; une pluralité de circuits de commutation; et une pluralité de trajets connectant chacun électriquement l'une de la pluralité de bornes d'entrée et l'une de la pluralité de bornes de sortie par l'intermédiaire de l'un de la pluralité de circuits de commutation, la pluralité de trajets comprenant des premier et second trajets se croisant dans une vue en plan de la surface principale du substrat, et dans une zone de croisement dans laquelle les premier et second trajets se croisent, le premier trajet est formé dans la première couche, le second trajet est formé dans la troisième couche, et aucun de la pluralité de trajets n'est formé dans la seconde couche.
(JA) 挿入損失の増大が抑制されるスイッチ装置を提供する。 スイッチ装置は、基板の主面上に順に積層された第1乃至第3層と、複数の入力端子と、複数の出力端子と、複数のスイッチ回路と、複数の経路であって、各経路は、複数のスイッチ回路の1つを通じて複数の入力端子の1つと複数の出力端子の1つとを電気的に接続する、複数の経路と、を備え、複数の経路は、基板の主面の平面視において交差する第1及び第2経路を含み、第1及び第2経路が交差する交差領域において、第1経路は第1層に形成され、第2経路は第3層に形成され、複数の経路のいずれも第2層に形成されていない。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)