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1. (WO2018159126) SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE
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Pub. No.: WO/2018/159126 International Application No.: PCT/JP2018/001143
Publication Date: 07.09.2018 International Filing Date: 17.01.2018
IPC:
H01L 27/088 (2006.01) ,H01L 21/762 (2006.01) ,H01L 27/144 (2006.01) ,H01L 27/146 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
762
Dielectric regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
146
Imager structures
Applicants:
ソニーセミコンダクタソリューションズ株式会社 SONY SEMICONDUCTOR SOLUTIONS CORPORATION [JP/JP]; 神奈川県厚木市旭町四丁目14番1号 4-14-1, Asahicho, Atsugi-shi, Kanagawa 2430014, JP
Inventors:
牛膓 哲雄 GOCHO, Tetsuo; JP
Agent:
特許業務法人つばさ国際特許事務所 TSUBASA PATENT PROFESSIONAL CORPORATION; 東京都新宿区新宿1丁目15番9号さわだビル3階 3F, Sawada Building, 15-9, Shinjuku 1-chome, Shinjuku-ku, Tokyo 1600022, JP
Priority Data:
2017-04070203.03.2017JP
Title (EN) SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEURS, PROCÉDÉ DE FABRICATION D'UN DISPOSITIF À SEMI-CONDUCTEURS ET DISPOSITIF ÉLECTRONIQUE
(JA) 半導体装置および半導体装置の製造方法並びに電子機器
Abstract:
(EN) A semiconductor device according to an embodiment of the present invention comprises: an SOI substrate on which a silicon substrate layer, a first insulating layer, and a semiconductor layer are laminated in the stated order; a first transistor provided on the semiconductor layer; a second transistor having a higher withstand voltage than does the first transistor, the second transistor being provided on the silicon substrate layer; and an element isolation film provided between the first transistor and the second transistor, the element isolation film being configured from a second insulating layer that is buried in an opening that passes through the semiconductor layer and the first insulating layer and reaches the inside of the silicon substrate layer, and a portion of the second insulating layer constituting a gate insulation film of the second transistor.
(FR) La présente invention concerne, selon un mode de réalisation, un dispositif à semi-conducteurs comprenant : un substrat SOI sur lequel une couche de substrat de silicium, une première couche isolante et une couche semi-conductrice sont stratifiées dans l'ordre indiqué ; un premier transistor disposé sur la couche semi-conductrice ; un second transistor ayant une tension de maintien supérieure à celle du premier transistor, le second transistor étant disposé sur la couche de substrat de silicium ; et un film d'isolation d'élément disposé entre le premier transistor et le second transistor, le film d'isolation d'élément étant configuré à partir d'une seconde couche isolante qui est enfouie dans une ouverture qui passe à travers la couche semi-conductrice et la première couche isolante et atteint l'intérieur de la couche de substrat de silicium, et une partie de la seconde couche isolante constituant un film d'isolation de grille du second transistor.
(JA) 本開示の一実施形態の半導体装置は、シリコン基板層、第1の絶縁層、および半導体層がこの順に積層されたSOI基板と、半導体層上に設けられた第1のトランジスタと、シリコン基板層上に設けられ、第1のトランジスタよりも高耐圧な第2のトランジスタと、第1のトランジスタと第2のトランジスタとの間に設けられた素子分離膜とを備え、素子分離膜は、半導体層および第1の絶縁層を貫通してシリコン基板層内に達する開口に埋設された第2の絶縁層によって構成され、第2の絶縁層の一部は、第2のトランジスタのゲート絶縁膜を構成している。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)