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1. (WO2018158650) SEMICONDUCTOR DEVICE AND DRIVE METHOD FOR SEMICONDUCTOR DEVICE
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Pub. No.: WO/2018/158650 International Application No.: PCT/IB2018/051015
Publication Date: 07.09.2018 International Filing Date: 20.02.2018
IPC:
H03K 19/00 (2006.01) ,H01L 21/822 (2006.01) ,H01L 27/04 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
19
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
Applicants:
株式会社半導体エネルギー研究所 SEMICONDUCTOR ENERGY LABORATORY CO., LTD. [JP/JP]; 神奈川県厚木市長谷398 398, Hase, Atsugi-shi, Kanagawa 2430036, JP
Inventors:
松嵜隆徳 MATSUZAKI, Takanori; JP
Priority Data:
2017-04031203.03.2017JP
Title (EN) SEMICONDUCTOR DEVICE AND DRIVE METHOD FOR SEMICONDUCTOR DEVICE
(FR) DISPOSITIF SEMI-CONDUCTEUR ET SON PROCÉDÉ DE COMMANDE
(JA) 半導体装置、および半導体装置の駆動方法
Abstract:
(EN) Provided is a semiconductor device that highly precisely generates stable negative potential and has been made to consume less power. The present invention has a voltage conversion circuit, a comparator, a logic circuit, a transistor, and a capacitive element. In accordance with a clock signal that is outputted by the logic circuit, the voltage conversion circuit outputs, as a second signal, a signal that is generated by converting the voltage of an inputted first signal. The supply or suspension of power-supply voltage to the comparator is controlled in accordance with a power-gating signal. When the transistor is not conducting, the transistor holds output voltage from the comparator in the capacitance element. When the power-supply voltage to the comparator is suspended, the logic circuit switches the supply or suspension of the clock signal on the basis of the voltage held by the capacitance element.
(FR) La présente invention concerne un dispositif semi-conducteur qui génère très précisément un potentiel négatif stable et est fabriqué de manière à consommer moins de courant. La présente invention comprend un circuit de conversion de tension, un comparateur, un circuit logique, un transistor et un élément capacitif. En fonction d'un signal d'horloge sorti par le circuit logique, le circuit de conversion de tension sort, à titre de second signal, un signal généré en convertissant la tension d'un premier signal entré. L'alimentation ou la suspension de la tension d'alimentation en courant destinée au comparateur est régulée en fonction d'un signal de réduction de courant. Lorsque le transistor n'est pas conducteur, le transistor maintient une tension de sortie provenant du comparateur dans l'élément capacitif. Lorsque la tension d'alimentation en courant destinée au comparateur est suspendue, le circuit logique commute l'alimentation ou la suspension du signal d'horloge sur la base de la tension maintenue dans l'élément capacitif.
(JA) 要約書 安定した負電位を高精度に生成するとともに、低消費電力化が図られた半導体装置を提供すること。 電圧変換回路と、コンパレータと、論理回路と、トランジスタと、容量素子と、を有する。電圧変換回路は、論 理回路が出力するクロック信号に応じて、入力される第1の信号の電圧を変換した信号を第2の信号として 出力する機能を有する。コンパレータは、パワーゲーティング信号に応じて電源電圧の供給または停止が 制御される機能を有する。トランジスタは、当該トランジスタを非導通状態とする期間において容量素子にコ ンパレータの出力電圧を保持する機能を有する。論理回路は、コンパレータへの電源電圧が停止する期間 において、容量素子に保持された電圧を基にクロック信号の供給または停止を切り替える機能を有する構 成とする。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)