Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2018158529) METHOD FOR MANUFACTURING A DONOR SUBSTRATE FOR MAKING OPTOELECTRONIC DEVICES
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/158529 International Application No.: PCT/FR2018/050446
Publication Date: 07.09.2018 International Filing Date: 26.02.2018
IPC:
H01L 21/02 (2006.01) ,H01L 33/00 (2010.01) ,H01L 21/762 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
762
Dielectric regions
Applicants:
SOITEC [FR/FR]; Parc Technologique des Fontaines Chemin des Franques 38190 BERNIN, FR
Inventors:
SOTTA, David; FR
Agent:
BREESE, Pierre; FR
Priority Data:
175166601.03.2017FR
Title (EN) METHOD FOR MANUFACTURING A DONOR SUBSTRATE FOR MAKING OPTOELECTRONIC DEVICES
(FR) PROCEDE DE FABRICATION D'UN SUBSTRAT DONNEUR POUR LA FORMATION DE DISPOSITIFS OPTOELECTRONIQUES
Abstract:
(EN) The invention relates to a method for preparing a crystalline semiconductor layer in order for the layer to be provided with a specific lattice parameter. Said method involves a relaxation procedure which is applied for a first time to a first starting donor substrate (1) in order to obtain a second donor substrate (5). Using the second donor substrate (5) as the starting donor substrate (1), the relaxation procedure is repeated for a number of times that is sufficient for the lattice parameter of the relaxed layer to be provided with the specific lattice parameter. The invention also relates to a set (10) of substrates (5') obtained by said method.
(FR) L'invention porte sur un procédé de préparation d'une couche de semi-conducteur cristallin pour qu'elle présente un paramètre de maille déterminé. Le procédé met en œuvre une séquence de relaxation appliquée une première fois sur un premier substrat donneur de départ (1) pour fournir un second substrat donneur (5). La séquence de relaxation est répétée, en prenant le second substrat donneur (5) comme substrat donneur de départ (1), un nombre suffisant de fois pour que le paramètre de maille de la couche relaxée présente le paramètre de maille déterminé. L'invention porte également sur une collection (10) de substrats (5' ) issus de ce procédé.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: French (FR)
Filing Language: French (FR)