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1. (WO2018158265) MEMORY ARRANGEMENT AND METHOD FOR OPERATING OR TESTING A MEMORY ARRANGEMENT

Pub. No.:    WO/2018/158265    International Application No.:    PCT/EP2018/054836
Publication Date: Sat Sep 08 01:59:59 CEST 2018 International Filing Date: Wed Feb 28 00:59:59 CET 2018
IPC: G11C 16/34
G11C 29/50
Applicants: AMS AG
Inventors: SCHATZBERGER, Gregor
LEISENBERGER, Friedrich Peter
SARSON, Peter
Title: MEMORY ARRANGEMENT AND METHOD FOR OPERATING OR TESTING A MEMORY ARRANGEMENT
Abstract:
A memory arrangement comprises a non-volatile memory plane (2), a replacement plane (3), an address select block (302), and a counter arrangement (300) having at least one counter (310 to 312). The at least one counter (310 to 312) is configured to be incremented at a write cycle of the memory arrangement (1). The address select block (302) is configured to switch from the non-volatile memory plane (2) to the replacement plane (3), if a counter value of the at least one counter (310 to 312) is higher than a predetermined limit.