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1. (WO2018158037) METHOD FOR PRODUCING PATTERNED LAYERS
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Pub. No.: WO/2018/158037 International Application No.: PCT/EP2018/052657
Publication Date: 07.09.2018 International Filing Date: 02.02.2018
IPC:
B82Y 10/00 (2011.01) ,H01B 1/02 (2006.01) ,H01L 21/027 (2006.01) ,H01L 21/033 (2006.01) ,H01L 21/308 (2006.01) ,H01L 51/00 (2006.01)
B PERFORMING OPERATIONS; TRANSPORTING
82
NANO-TECHNOLOGY
Y
SPECIFIC USES OR APPLICATIONS OF NANO-STRUCTURES; MEASUREMENT OR ANALYSIS OF NANO-STRUCTURES; MANUFACTURE  OR TREATMENT OF NANO-STRUCTURES
10
Nano-technology for information processing, storage or transmission, e.g. quantum computing or single electron logic
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
B
CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
1
Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
02
mainly consisting of metals or alloys
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
027
Making masks on semiconductor bodies for further photolithographic processing, not provided for in group H01L21/18 or H01L21/34165
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
027
Making masks on semiconductor bodies for further photolithographic processing, not provided for in group H01L21/18 or H01L21/34165
033
comprising inorganic layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
308
using masks
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
51
Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
Applicants:
EVONIK DEGUSSA GMBH [DE/DE]; Rellinghauser Straße 1-11 45128 Essen, DE
Inventors:
MEYER, Sebastian; DE
MERKULOV, Sonja; DE
PFEIFER, Holger; DE
RENNER, Gerhard; DE
Priority Data:
17158423.828.02.2017EP
Title (EN) METHOD FOR PRODUCING PATTERNED LAYERS
(FR) PROCÉDÉ DE PRODUCTION DE COUCHES STRUCTURÉES
(DE) VERFAHREN ZUR HERSTELLUNG STRUKTURIERTER SCHICHTEN
Abstract:
(EN) The present invention relates to a method for producing a patterned layer comprising the following steps in ascending order: i) providing a substrate, ii) applying a polymeric sacrificial layer to the substrate, iii) applying an inorganic or organic-inorganic masking layer to the sacrificial layer, iv) patterning the masking layer by supplying energy, v) if appropriate etching the sacrificial layer. The present invention furthermore relates to the patterned layer obtainable or obtained by this method. The present invention additionally relates to a method for producing a coated substrate comprising steps i) to v) in ascending order, and to the coated substrate obtainable or obtained by this method. The present invention also relates to the use of the patterned layer as a template for correspondingly patterned deposition of metals.
(FR) Cette invention concerne un procédé pour produire une couche structurée comprenant, dans l'ordre croissant suivant, les étapes consistant : i) à fournir un substrat, ii) à appliquer une couche sacrificielle polymère sur le substrat, iii) à appliquer une couche masquante inorganique ou organo-inorganique sur la couche sacrificielle, iv) à structurer la couche masquante par apport d'énergie, v) à éventuellement attaquer la couche sacrificielle. Cette invention concerne en outre la couche structurée pouvant être ou étant obtenue au moyen de ce procédé. La présente invention concerne en outre un procédé pour produire un substrat ainsi pourvu de couches, comprenant les étapes i) à v) réalisées dans l'ordre croissant, ainsi que le substrat pourvu de couches pouvant être ou étant obtenu au moyen de ce procédé. Cette invention concerne également l'utilisation de la couche structurée en tant que gabarit pour réaliser un dépôt ainsi structuré de métaux.
(DE) Die vorliegende Erfindung betrifft ein Verfahren zur Herstellung einer strukturierten Schicht umfassend die nachfolgenden Schritte in aufsteigender Reihenfolge: i) Bereitstellen eines Substrats, ii) Aufbringen einer polymeren Opferschicht auf das Substrat, iii) Aufbringen einer anorganischen oder organisch-anorganischen Maskierungsschicht auf die Opferschicht, iv) Strukturierung der Maskierungsschicht durch Energiezufuhr, v) ggf. Ätzen der Opferschicht. Sie betrifft ferner die durch dieses Verfahren erhältliche oder erhaltene strukturierte Schicht. Die vorliegende Erfindung betrifft außerdem ein Verfahren zur Herstellung eines beschichteten Substrats umfassend die Schritte i) bis v) in austeigender Reihenfolge sowie das durch dieses Verfahren erhältliche oder erhaltene beschichtete Substrat. Die vorliegende Erfindung betrifft auch die Verwendung der strukturierten Schicht als Templat zu entsprechend strukturierten Deposition von Metallen.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: German (DE)
Filing Language: German (DE)