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1. (WO2018157546) PACKAGING METHOD FOR PACKAGE INTEGRATED WITH POWER TRANSMISSION SYSTEM
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/157546 International Application No.: PCT/CN2017/095386
Publication Date: 07.09.2018 International Filing Date: 01.08.2017
IPC:
H01L 21/50 (2006.01) ,H01L 21/60 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
Applicants: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION[CN/CN]; No.78 Changshan Avenue JiangYin, Jiangsu 214437, CN
Inventors: LIN, Johnson; CN
LIN, Alan; CN
HO, Patrick; CN
ZHOU, Zuyuan; CN
Agent: J.Z.M.C. PATENT AND TRADEMARK LAW OFFICE; Yu Mingwei, Room5022 No.335 Guo Ding Road Yangpu District Shanghai 200433, CN
Priority Data:
201710124760.703.03.2017CN
Title (EN) PACKAGING METHOD FOR PACKAGE INTEGRATED WITH POWER TRANSMISSION SYSTEM
(FR) PROCÉDÉ DE MISE SOUS BOÎTIER POUR BOÎTIER INTÉGRÉ À UN SYSTÈME DE TRANSMISSION DE PUISSANCE
(ZH) 集成有供电传输系统的封装件的封装方法
Abstract:
(EN) A packaging method for a package integrated with a power transmission system, comprising the following steps of: 1) providing a carrier (11); 2) forming, employing an electroplating process, first metal connection posts (12) on the surface of the carrier (11); 3) providing an active module (14) and a passive module (15) on the surface, formed with the first metal connection posts (12), of the carrier (11), and forming second metal connection posts (16) on the surfaces of the active module (14) and the passive module (15); 4) packaging and molding the first metal connection posts (12), the active module (14), the passive module (15), and the second metal connection posts (16); 5) forming a re-wiring layer (18) on the surface of plastic-packaging material (17); 6) providing an electricity chip (19) on the surface of the re-wiring layer (18), the electricity chip (19) butting a low voltage power rail by means of a plurality of micro bumps (20); and 7) peeling the carrier (11), to form solder bumps (23) connected to the first metal connection posts (12). By means of using a three-dimensional chip stacking technology, power transmission efficiency is improved and the number of different available voltage rails is increased.
(FR) L'invention concerne un procédé de mise sous boîtier pour un boîtier intégré à un système de transmission de puissance, comprenant les étapes suivantes consistant à : 1) fournir un support (11) ; 2) former, à l'aide d'un procédé d'électrodéposition, des premières bornes de connexion métalliques (12) sur la surface du support (11) ; 3) fournir un module actif (14) et un module passif (15) sur la surface, formés avec les premières bornes de connexion métalliques (12), du support (11), et former des secondes bornes de connexion métalliques (16) sur les surfaces du module actif (14) et du module passif (15) ; 4) mettre sous boîtier et mouler les premières bornes de connexion métalliques (12), le module actif (14), le module passif (15) et les secondes bornes de connexion métalliques (16) ; 5) former une couche de recâblage (18) sur la surface du matériau de mise sous boîtier en plastique (17) ; 6) fournir une puce électrique (19) sur la surface de la couche de recâblage (18), la puce électrique (19) venant en butée contre un rail d'alimentation basse tension au moyen d'une pluralité de microbosses (20) ; et 7) peler le support (11), pour former des bosses de soudure (23) connectées aux premières bornes de connexion métalliques (12). En utilisant une technologie d'empilement de puce tridimensionnelle, l'efficacité de transmission d'énergie est améliorée et le nombre de différents rails de tension disponibles est augmenté.
(ZH) 一种集成有供电传输系统的封装件的封装方法,包括如下步骤:1)提供一载体(11);2)采用电镀工艺在载体(11)表面形成第一金属连接柱(12);3)将有源模块(14)及无源模块(15)设置于载体(11)形成有第一金属连接柱(12)的表面上,并在有源模块(14)及所述无源模块(15)表面形成第二金属连接柱(16);4)将第一金属连接柱(12)、有源模块(14)、无源模块(15)及第二金属连接柱(16)封装成型;5)在塑封材料(17)表面形成再布线层(18);6)将用电芯片(19)设置于再布线层(18)表面,用电芯片(19)经由多个微凸块(20)实现与低电压供电轨道的对接;7)剥离载体(11),形成与第一金属连接柱(12)相连接的焊料凸块(23)。通过使用三维芯片堆叠技术,提高了电力输送效率,增加了不同电压轨道的可用数量。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)