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1. WO2018152952 - READOUT CIRCUIT AND READOUT METHOD FOR THREE-DIMENSIONAL MEMORY

Publication Number WO/2018/152952
Publication Date 30.08.2018
International Application No. PCT/CN2017/081816
International Filing Date 25.04.2017
IPC
G11C 7/10 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 5/02 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
02Disposition of storage elements, e.g. in the form of a matrix array
G11C 7/06 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
06Sense amplifiers; Associated circuits
CPC
G11C 13/0004
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
13Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
0002using resistive RAM [RRAM] elements
0004comprising amorphous/crystalline phase transition cells
G11C 13/0026
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
13Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
0002using resistive RAM [RRAM] elements
0021Auxiliary circuits
0023Address circuits or decoders
0026Bit-line or column circuits
G11C 13/0028
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
13Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
0002using resistive RAM [RRAM] elements
0021Auxiliary circuits
0023Address circuits or decoders
0028Word-line or row circuits
G11C 13/003
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
13Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
0002using resistive RAM [RRAM] elements
0021Auxiliary circuits
003Cell access
G11C 13/0038
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
13Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
0002using resistive RAM [RRAM] elements
0021Auxiliary circuits
0038Power supply circuits
G11C 13/004
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
13Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
0002using resistive RAM [RRAM] elements
0021Auxiliary circuits
004Reading or sensing circuits or methods
Applicants
  • 中国科学院上海微系统与信息技术研究所 SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES [CN]/[CN]
Inventors
  • 雷宇 LEI, Yu
  • 陈后鹏 CHEN, Houpeng
  • 宋志棠 SONG, Zhitang
Agents
  • 上海光华专利事务所 J.Z.M.C. PATENT AND TRADEMARK LAW OFFICE
Priority Data
201710092925.721.02.2017CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) READOUT CIRCUIT AND READOUT METHOD FOR THREE-DIMENSIONAL MEMORY
(FR) CIRCUIT DE LECTURE ET PROCÉDÉ DE LECTURE POUR MÉMOIRE TRIDIMENSIONNELLE
(ZH) 一种三维存储器读出电路及读出方法
Abstract
(EN) The present invention provides a readout circuit and readout method for a three-dimensional memory. The readout circuit comprises: a read reference circuit used for producing read reference current capable of quickly distinguishing read low resistance state unit current and read high resistance state unit current; and a sensitive amplifier. The read reference circuit comprises a reference unit, a bit line matching module, a word line matching module, and a transmission gate parasitic parameter matching module. In the present invention, for the parasitic effect and electric leakage of a three-dimensional memory in plane and vertical directions, the matching of bit line parasitic parameters, electric leakage and transmission gate parasitic parameters is introduced into the read reference current, the matching of current mirror parasitic parameters is introduced into read current, a pseudo-read phenomenon is eliminated, and the readout time is shortened; and the application range is wide, and the readout accuracy is high.
(FR) La présente invention concerne un circuit de lecture et un procédé de lecture pour une mémoire tridimensionnelle. Le circuit de lecture comprend : un circuit de référence de lecture utilisé pour produire un courant de référence de lecture capable de distinguer rapidement un courant d'unité d'état de résistance basse de lecture et un courant d'unité d'état de résistance élevée de lecture; et un amplificateur sensible. Le circuit de référence de lecture comprend une unité de référence, un module de mise en correspondance de lignes de bits, un module de mise en correspondance de lignes de mots et un module de mise en correspondance de paramètres parasites de grille de transmission. Dans la présente invention, pour l'effet parasite et la fuite électrique d'une mémoire tridimensionnelle dans des directions planes et verticales, la mise en correspondance de paramètres parasites de ligne de bits, de fuite électrique et de paramètres parasites de grille de transmission est introduite dans le courant de référence de lecture, la mise en correspondance des paramètres parasites de miroir de courant est introduite en courant de lecture, un phénomène de pseudo-lecture est éliminé, et le temps de lecture est raccourci; et la plage d'application est large, et la précision de lecture est élevée.
(ZH) 本发明提供一种三维存储器读出电路及读出方法,包括:读参考电路,产生一个可以快速区分读低阻态单元电流和读高阻态单元电流的读参考电流;以及灵敏放大器。读参考电路包括参考单元、位线匹配模块、字线匹配模块和传输门寄生参数匹配模块。本发明针对三维存储器在平面和垂直方向的寄生效应和漏电,在读参考电流中引入对位线寄生参数、漏电和传输门寄生参数的匹配,在读电流中引入对电流镜寄生参数的匹配,消除了伪读取现象,减小了读出时间;且适用范围广、读出正确率高。
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