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1. WO2018151189 - COMPOUND SEMICONDUCTOR LAMINATE SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND SEMICONDUCTOR ELEMENT

Publication Number WO/2018/151189
Publication Date 23.08.2018
International Application No. PCT/JP2018/005169
International Filing Date 15.02.2018
IPC
H01L 21/02 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
CPC
H01L 21/02
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/02002
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02002Preparing wafers
H01L 21/02008
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02002Preparing wafers
02005Preparing bulk and homogeneous wafers
02008Multistep processes
H01L 21/02021
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02002Preparing wafers
02005Preparing bulk and homogeneous wafers
02008Multistep processes
0201Specific process step
02021Edge treatment, chamfering
H01L 21/0242
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02365Forming inorganic semiconducting materials on a substrate
02367Substrates
0237Materials
0242Crystalline insulating materials
H01L 21/02428
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02365Forming inorganic semiconducting materials on a substrate
02367Substrates
02428Structure
Applicants
  • 信越化学工業株式会社 SHIN-ETSU CHEMICAL CO., LTD. [JP]/[JP]
  • 株式会社CUSIC CUSIC INC. [JP]/[JP]
Inventors
  • 長澤 弘幸 NAGASAWA Hiroyuki
  • 久保田 芳宏 KUBOTA Yoshihiro
  • 秋山 昌次 AKIYAMA Shoji
Agents
  • 特許業務法人英明国際特許事務所 PATENT PROFESSIONAL CORPORATION EI-MEI PATENT OFFICE
Priority Data
2017-02706916.02.2017JP
Publication Language Japanese (ja)
Filing Language Japanese (JA)
Designated States
Title
(EN) COMPOUND SEMICONDUCTOR LAMINATE SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND SEMICONDUCTOR ELEMENT
(FR) SUBSTRAT STRATIFIÉ SEMI-CONDUCTEUR COMPOSÉ, SON PROCÉDÉ DE FABRICATION, ET ÉLÉMENT SEMI-CONDUCTEUR
(JA) 化合物半導体積層基板及びその製造方法、並びに半導体素子
Abstract
(EN) A compound semiconductor laminate substrate comprising two single-crystalline compound semiconductor substrates directly bonded together and laminated, the single-crystalline compound semiconductor substrates having the same composition including A and B as constituent elements and having the same atomic arrangement, characterized in that the front and back surfaces of the laminate substrate are polar faces comprising the same kind of atoms of A or B, and that a laminate interface comprises a bond of atoms of either B or A and is a unipolar anti-phase region boundary plane in which the crystal lattices of the atoms are matched. In this way, the polar faces of the front and rear surfaces of the compound semiconductor laminate substrate are made monopolar, thereby facilitating semiconductor element process designing, and making it possible to manufacture a low-cost, high-performance, and stable semiconductor element without implementing complex substrate processing.
(FR) La présente invention concerne un substrat stratifié semi-conducteur composé comprenant deux substrats semi-conducteurs composés monocristallins directement liés ensemble et stratifiés, les substrats semi-conducteurs composés monocristallins ayant la même composition comprenant A et B en tant qu'éléments constitutifs et ayant le même agencement atomique, caractérisé en ce que les surfaces avant et arrière du substrat stratifié sont des faces polaires comprenant le même type d'atomes d'A ou B, et qu'une interface de stratifié comprend une liaison d'atomes d'A ou B et est un plan de limite de région anti-phase unipolaire dans lequel les réseaux cristallins des atomes sont appariés. De cette manière, les faces polaires des surfaces avant et arrière du substrat stratifié semi-conducteur composé sont rendues monopolaires, facilitant ainsi la conception de processus d'élément semi-conducteur, et permettant de fabriquer un élément semi-conducteur stable, à haute performance et à faible coût sans mettre en œuvre de traitement de substrat complexe.
(JA) A及びBを構成元素として含む同一組成で同一の原子配列を有する2枚の単結晶の化合物半導体基板が直接貼り合わされて積層された基板であって、その積層基板の表裏面がA又はBの同種の原子からなる極性面であり、積層界面がB又はAのいずれか一方の原子同士の結合からなると共にそれらの結晶格子が整合している単極性の反位相領域境界面であることを特徴とする化合物半導体積層基板である。これにより化合物半導体積層基板の表裏面の極性面を単一極性として半導体素子の工程設計を容易にすると共に、複雑な基板加工を施すこと無く、低コストで高性能で安定な半導体素子の製造を可能とする。
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