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1. (WO2018150537) SUBSTRATE TREATMENT DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND PROGRAM
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Pub. No.: WO/2018/150537 International Application No.: PCT/JP2017/005888
Publication Date: 23.08.2018 International Filing Date: 17.02.2017
IPC:
H01L 21/31 (2006.01) ,H01L 21/22 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
22
Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant
Applicants:
株式会社KOKUSAI ELECTRIC KOKUSAI ELECTRIC CORPORATION [JP/JP]; 東京都千代田区神田鍛冶町三丁目4番地 3-4, Kandakaji-cho, Chiyoda-ku, TOKYO 1010045, JP
Inventors:
西堂 周平 SAIDO Shuhei; JP
山口 天和 YAMAGUCHI Takatomo; JP
佐々木 隆史 SASAKI Takafumi; JP
Priority Data:
Title (EN) SUBSTRATE TREATMENT DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND PROGRAM
(FR) DISPOSITIF DE TRAITEMENT DE SUBSTRAT, PROCÉDÉ DE FABRICATION DE DISPOSITIF À SEMICONDUCTEUR, ET PROGRAMME
(JA) 基板処理装置、半導体装置の製造方法およびプログラム
Abstract:
(EN) [Problem] The present invention addresses the problem of improving productivity by shortening the time for increasing the temperature inside of a treatment chamber, and by eliminating a dummy wafer. [Solution] This substrate treatment device is provided with: a reaction container that stores therein a substrate holding body that holds substrates; a lid section that closes an opening at a reaction container lower end; and a cover section covering the lid section. The cover section has: an inner high section formed to protrude to the inside of the reaction container; and a flange section, which is formed at a lower end of the inner high section, and which is disposed between the lid section and the reaction container. A heat insulating section is disposed in a hollow part inside the inner high section, and a heating section is disposed between the heat insulating section and the inner high section.
(FR) Le problème décrit par la présente invention est d'améliorer la productivité en raccourcissant le temps pour augmenter la température à l'intérieur d'une chambre de traitement, et en éliminant une plaquette factice. La solution selon l'invention porte sur un dispositif de traitement de substrat comprenant : une cuve de réaction qui stocke en son sein un corps de support de substrat qui maintient des substrats; une section de couvercle qui ferme une ouverture au niveau d'une extrémité inférieure de cuve de réaction; et une section de couvercle recouvrant la section de couvercle. La section de couvercle a : une section haute interne formée pour faire saillie vers l'intérieur de la cuve de réaction; et une section de bride, qui est formée au niveau d'une extrémité inférieure de la section haute interne, et qui est disposée entre la section de couvercle et la cuve de réaction. Une section d'isolation thermique est disposée dans une partie creuse à l'intérieur de la section haute interne, et une section de chauffage est disposée entre la section d'isolation thermique et la section haute interne.
(JA) [課題] 処理室内の昇温時間を短くし、かつ、ダミーウエハをなくすことにより生産性を向上させる。 [解決手段] 基板を保持する基板保持体を内部に収容する反応容器と、反応容器下端の開口部を閉塞する蓋部と、蓋部を覆うカバー部と、を備え、カバー部は、反応容器内に突出するように形成された中高部と、中高部の下端に形成され、蓋部および反応容器との間に配置されるフランジ部と、を有し、中高部の内側の中空部分には断熱部が設置され、断熱部と中高部との間には加熱部が設置される。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)