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1. WO2018150504 - OPERATION VERIFICATION APPARATUS, OPERATION VERIFICATION METHOD, AND OPERATION VERIFICATION PROGRAM

Publication Number WO/2018/150504
Publication Date 23.08.2018
International Application No. PCT/JP2017/005633
International Filing Date 16.02.2017
IPC
G06F 11/36 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
36Preventing errors by testing or debugging of software
CPC
G06F 11/36
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
36Preventing errors by testing or debugging software
G06F 11/3632
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
36Preventing errors by testing or debugging software
362Software debugging
3632of specific synchronisation aspects
G06F 11/3688
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
36Preventing errors by testing or debugging software
3668Software testing
3672Test management
3688for test execution, e.g. scheduling of test suites
G06F 8/75
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
8Arrangements for software engineering
70Software maintenance or management
75Structural analysis for program understanding
G06F 9/3816
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3802Instruction prefetching
3816Instruction alignment, e.g. cache line crossing
G06F 9/4881
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
48Program initiating; Program switching, e.g. by interrupt
4806Task transfer initiation or dispatching
4843by program, e.g. task dispatcher, supervisor, operating system
4881Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
Applicants
  • 三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP]/[JP]
Inventors
  • 磯田 誠 ISODA, Makoto
Agents
  • 溝井国際特許業務法人 MIZOI INTERNATIONAL PATENT FIRM
Priority Data
Publication Language Japanese (ja)
Filing Language Japanese (JA)
Designated States
Title
(EN) OPERATION VERIFICATION APPARATUS, OPERATION VERIFICATION METHOD, AND OPERATION VERIFICATION PROGRAM
(FR) APPAREIL DE VÉRIFICATION D'OPÉRATION, PROCÉDÉ DE VÉRIFICATION D'OPÉRATION ET PROGRAMME DE VÉRIFICATION D'OPÉRATION
(JA) 動作検証装置、動作検証方法および動作検証プログラム
Abstract
(EN) A division unit (110) divides a plurality of control processes for each of a first program (61), before change, and a second program (62), after change, into a concurrent process and a function serial process, and outputs the concurrent process and the function serial process as a first divided program (71) and a second divided program (72). In addition, when a functional defect is detected, a cause estimation unit (150) estimates, as a cause of the functional defect, function serial processes that are different between the first divided program (71) and the second divided program (72). When a defect is detected as a concurrent defect, the cause estimation unit (150) estimates, as a cause of the concurrent defect, concurrent processes that are different between the first divided program (71) and the second divided program (72).
(FR) L'invention concerne une unité de division (110) qui divise une pluralité de processus de commande pour chacun d'un premier programme (61), avant changement, et d'un second programme (62), après changement, en un processus simultané et un processus en série de fonctions, et délivre en sortie le processus simultané et le processus en série de fonctions sous la forme d'un premier programme divisé (71) et d'un second programme divisé (72). En outre, lorsqu'un défaut fonctionnel est détecté, une unité d'estimation de cause (150) estime, en tant que cause du défaut fonctionnel, des processus en série de fonctions qui sont différents entre le premier programme divisé (71) et le second programme divisé (72). Lorsqu'un défaut est détecté en tant que défaut simultané, l'unité d'estimation de cause (150) estime, en tant que cause du défaut simultané, des processus simultanés qui sont différents entre le premier programme divisé (71) et le second programme divisé (72).
(JA) 分割部(110)が、変更前の第1のプログラム(61)と変更後の第2のプログラム(62)との各々について、複数の制御処理の各々を、並行性処理と機能逐次処理とに分割し、第1の分割済プログラム(71)と第2の分割済プログラム(72)として出力する。また、原因推定部(150)が、機能的欠陥が検出された場合に、第1の分割済プログラム(71)と第2の分割済プログラム(72)との間で異なる機能逐次処理を機能的欠陥の原因と推定する。原因推定部(150)が、欠陥が並行性欠陥として検出された場合に、第1の分割済プログラム(71)と第2の分割済プログラム(72)との間で異なる並行性処理を並行性欠陥の原因と推定する。
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