Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2018146965) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/146965 International Application No.: PCT/JP2017/046637
Publication Date: 16.08.2018 International Filing Date: 26.12.2017
IPC:
H01L 27/146 (2006.01) ,H01L 21/3205 (2006.01) ,H01L 21/768 (2006.01) ,H01L 21/8234 (2006.01) ,H01L 23/522 (2006.01) ,H01L 27/00 (2006.01) ,H01L 27/088 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
146
Imager structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
Applicants:
ソニーセミコンダクタソリューションズ株式会社 SONY SEMICONDUCTOR SOLUTIONS CORPORATION [JP/JP]; 神奈川県厚木市旭町四丁目14番1号 4-14-1, Asahi-cho, Atsugi-shi, Kanagawa 2430014, JP
Inventors:
天野 茂樹 AMANO, Shigeki; JP
Agent:
亀谷 美明 KAMEYA, Yoshiaki; JP
金本 哲男 KANEMOTO, Tetsuo; JP
萩原 康司 HAGIWARA, Yasushi; JP
Priority Data:
2017-02185309.02.2017JP
Title (EN) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMICONDUCTEURS ET PROCÉDÉ DE FABRICATION D'UN DISPOSITIF À SEMICONDUCTEURS
(JA) 半導体装置、および半導体装置の製造方法
Abstract:
(EN) [Problem] The present invention addresses the problem of providing a semiconductor device wherein a terminal for outputting electrical signals to the outside is further miniaturized, and a method for manufacturing the semiconductor device. [Solution] This semiconductor device is provided with: a first chip, which is formed by laminating a first substrate and a first wiring layer, and which includes a sensor element; a second chip, which is formed by laminating a second substrate and a second wiring layer, and which is bonded to the first chip such that the first wiring layer and the second wiring layer face each other; and at least one through hole via, which is electrically connected to the second wiring layer, and which protrudes from a second chip surface by penetrating the second substrate, said second chip surface being on the reverse side of the surface to which the first chip is laminated.
(FR) Le problème décrit par la présente invention est de fournir un dispositif à semi-conducteurs dans lequel une borne destinée à émettre des signaux électriques vers l'extérieur est en outre miniaturisée, et un procédé de fabrication du dispositif à semi-conducteurs. La solution selon l'invention porte sur un dispositif à semi-conducteurs qui est pourvu : d'une première puce, qui est formée par stratification d'un premier substrat et d'une première couche de câblage, et qui comprend un élément de capteur ; d'une seconde puce, qui est formée par stratification d'un second substrat et d'une seconde couche de câblage, et qui est liée à la première puce de telle sorte que la première couche de câblage et la seconde couche de câblage se font face ; et au moins un trou d'interconnexion traversant, qui est électriquement connecté à la seconde couche de câblage, et qui fait saillie à partir d'une seconde surface de puce en pénétrant dans le second substrat, ladite seconde surface de puce se trouvant sur le côté inverse de la surface sur laquelle la première puce est stratifiée.
(JA) 【課題】外部に電気信号を出力する端子がより微細化された半導体装置、および半導体装置の製造方法を提供する。 【解決手段】第1基板および第1配線層を積層して形成され、センサ素子を含む第1チップと、第2基板および第2配線層を積層して形成され、前記第1配線層および前記第2配線層が互いに対向するように前記第1チップと貼り合わされた第2チップと、前記第2配線層と電気的に接続し、前記第2基板を貫通することで、前記第1チップが積層された面と対向する前記第2チップの面から突出する少なくとも1つ以上のスルーホールビアと、を備える、半導体装置。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)