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1. (WO2018146449) CACHE BYPASS

Pub. No.:    WO/2018/146449    International Application No.:    PCT/GB2018/050213
Publication Date: Fri Aug 17 01:59:59 CEST 2018 International Filing Date: Fri Jan 26 00:59:59 CET 2018
IPC: G06F 12/0811
G06F 12/0888
Applicants: ARM LIMITED
Inventors: JALAL, Jamshed
FILIPPO, Michael
MATHEWSON, Bruce James
MANNAVA, Phanindra Kumar
Title: CACHE BYPASS
Abstract:
A data processing apparatus is provided including a memory hierarchy having a plurality of cache levels including a forwarding cache level, at least one bypassed cache level, and a receiver cache level. The forwarding cache level forwards a data access request relating to a given data value to the receiver cache level, inhibiting the at least one bypassed cache level from responding to the data access request. The receiver cache level includes presence determination circuitry for performing a determination as to whether the given data value is present in the at least one bypassed cache level. In response to the determination indicating that the data value is present in the at least one bypassed cache level, one of the at least one bypassed cache level is made to respond to the data access request.