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1. (WO2018144957) 3D SEMICONDUCTOR DEVICE AND STRUCTURE
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Pub. No.: WO/2018/144957 International Application No.: PCT/US2018/016759
Publication Date: 09.08.2018 International Filing Date: 03.02.2018
IPC:
H01L 27/11551 (2017.01) ,H01L 27/11524 (2017.01) ,H01L 27/11529 (2017.01) ,H01L 27/06 (2006.01)
[IPC code unknown for ERROR IPC Code incorrect: invalid subgroup (0=>999999)!][IPC code unknown for ERROR IPC Code incorrect: invalid subgroup (0=>999999)!][IPC code unknown for ERROR IPC Code incorrect: invalid subgroup (0=>999999)!]
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
06
including a plurality of individual components in a non-repetitive configuration
Applicants:
MONOLITHIC 3D INC. [US/US]; 3555 Woodford Drive San Jose, California 95124, US
Inventors:
OR-BACH, Zvi; US
HAN, Jin-Woo; US
LUSKY, Eli; IL
Agent:
TRAN, Bao; US
Priority Data:
62/454,78504.02.2017US
62/468,37208.03.2017US
62/473,30817.03.2017US
62/484,28411.04.2017US
62/488,75722.04.2017US
62/501,13604.05.2017US
62/517,95911.06.2017US
62/523,76022.06.2017US
62/531,88013.07.2017US
62/539,05431.07.2017US
62/625,96102.02.2018US
Title (EN) 3D SEMICONDUCTOR DEVICE AND STRUCTURE
(FR) DISPOSITIF TRIDIMENSIONNEL À SEMI-CONDUCTEUR ET STRUCTURE
Abstract:
(EN) A 3D device, the device including: at least four active transistor layers, each layer including a plurality of transistors; and at least one per-layer programmable contact for each layer of the at least four active transistor layers.
(FR) La présente invention concerne un dispositif 3D, le dispositif comprenant : au moins quatre couches de transistors actifs, chaque couche comprenant une pluralité de transistors; et au moins un contact programmable par couche pour chaque couche des au moins quatre couches de transistors actifs.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)