Search International and National Patent Collections

1. (WO2018144956) THREE-DIMENSIONAL CALIBRATION STRUCTURES AND METHODS FOR MEASURING BURIED DEFECTS ON A THREE-DIMENSIONAL SEMICONDUCTOR WAFER

Pub. No.:    WO/2018/144956    International Application No.:    PCT/US2018/016758
Publication Date: Fri Aug 10 01:59:59 CEST 2018 International Filing Date: Sun Feb 04 00:59:59 CET 2018
IPC: H01L 21/66
H01L 21/67
Applicants: KLA-TENCOR CORPORATION
Inventors: MEASOR, Philip
DANEN, Robert M.
Title: THREE-DIMENSIONAL CALIBRATION STRUCTURES AND METHODS FOR MEASURING BURIED DEFECTS ON A THREE-DIMENSIONAL SEMICONDUCTOR WAFER
Abstract:
A three-dimensional calibration structure for measuring buried defects on a semiconductor device is disclosed. The three-dimensional calibration structure includes a defect standard wafer (DSW) including one or more programmed surface defects. The three-dimensional calibration structure includes a planarized layer deposited on the DSW. The three-dimensional calibration structure includes a layer stack deposited on the planarized layer. The layer stack includes two or more alternating layers. The three-dimensional calibration structure includes a cap layer deposited on the layer stack. One or more air gaps are formed in the layer stack following deposition of the cap layer. The three-dimensional calibration structure includes one or more holes formed into at least one of the cap layer, the layer stack, or the planarized layer.