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1. (WO2018144583) INTERRUPT HANDLING METHOD AND APPARATUS FOR SLOW PERIPHERALS
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Pub. No.: WO/2018/144583 International Application No.: PCT/US2018/016206
Publication Date: 09.08.2018 International Filing Date: 31.01.2018
IPC:
G06F 9/48 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
46
Multiprogramming arrangements
48
Programme initiating; Programme switching, e.g. by interrupt
Applicants:
TEXAS INSTRUMENTS INCORPORATED [US/US]; P.O. Box 655474, Mail Station 3999 Dallas, TX 75265-5474, US
TEXAS INSTRUMENTS JAPAN LIMITED [JP/JP]; 24-1, Nishi-Shinjuku 6-chome Shinjuku-ku Tokyo, 160-8366, JP (JP)
Inventors:
SONI, Maneesh; IN
SUVARNA, Rajeev; IN
KHARE, Nikunj; IN
Agent:
DAVIS, Michael, A., Jr.; US
ALBIN, Gregory, J.; US
Priority Data:
15/420,26731.01.2017US
Title (EN) INTERRUPT HANDLING METHOD AND APPARATUS FOR SLOW PERIPHERALS
(FR) PROCÉDÉ ET APPAREIL DE GESTION D'INTERRUPTION POUR PÉRIPHÉRIQUES LENTS
Abstract:
(EN) Described examples include interrupt handling circuitry (100) and methods for managing interrupts of a fast clock domain circuit (101) operated according to a first clock signal (FCLK) by a slow clock domain circuit (102) operated according to a second clock signal (SCLK) in which an interrupt generator circuit (110) generates an interrupt input signal (INT_IN) synchronized to the second clock signal (SCLK), and an interrupt clear circuit (114, 116) selectively resets the interrupt generator circuit (110) in response to an acknowledgment signal (ACK) from the first circuit (101) asynchronously with respect to the second clock signal (SCLK).
(FR) Des exemples décrits comprennent un circuit de gestion d'interruption (100) et des procédés de gestion d'interruptions d'un circuit de domaine d'horloge rapide (101) actionné selon un premier signal d'horloge (FCLK) par un circuit à domaine d'horloge lent (102) actionné selon un second signal d'horloge (SCLK) dans lequel un circuit générateur d'interruption (110) génère un signal d'entrée d'interruption (INT_IN) synchronisé avec le second signal d'horloge (SCLK), et un circuit d'interruption d'interruption (114, 116) réinitialise sélectivement le circuit de générateur d'interruption (110) en réponse à un signal d'accusé de réception (ACK) provenant du premier circuit (101) de manière asynchrone par rapport au second signal d'horloge (SCLK).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)