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1. (WO2018144538) NAND MEMORY ARRAYS, AND METHODS OF FORMING NAND MEMORY ARRAYS

Pub. No.:    WO/2018/144538    International Application No.:    PCT/US2018/016144
Publication Date: Fri Aug 10 01:59:59 CEST 2018 International Filing Date: Thu Feb 01 00:59:59 CET 2018
IPC: H01L 27/11556
H01L 27/11524
H01L 27/11529
H01L 27/11582
H01L 27/11568
H01L 27/1157
Applicants: MICRON TECHNOLOGY, INC.
Inventors: GODA, Akira
HU, Yushi
Title: NAND MEMORY ARRAYS, AND METHODS OF FORMING NAND MEMORY ARRAYS
Abstract:
Some embodiments include a NAND memory array which has a vertical stack of alternating insulative levels and wordline levels The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels, and is spaced form the control gate regions by charge-blocking material. The charge-trapping material along vertically adjacent wordline levels is spaced by intervening regions through which charge migration is impeded Channel material extends vertically along the stack and is spaced from the charge-trapping material by charge-tunneling material. Some embodiments include methods of forming NAND memory arrays.