WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Search
 
Browse
 
Translate
 
Options
 
News
 
Login
 
Help
 
Machine translation
1. (WO2018144538) NAND MEMORY ARRAYS, AND METHODS OF FORMING NAND MEMORY ARRAYS
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/144538 International Application No.: PCT/US2018/016144
Publication Date: 09.08.2018 International Filing Date: 31.01.2018
IPC:
H01L 27/11556 (2017.01) ,H01L 27/11524 (2017.01) ,H01L 27/11529 (2017.01) ,H01L 27/11582 (2017.01) ,H01L 27/11568 (2017.01) ,H01L 27/1157 (2017.01)
Applicants: MICRON TECHNOLOGY, INC.[US/US]; 8000 South Federal Way Boise, ID 83716, US
Inventors: GODA, Akira; US
HU, Yushi; US
Agent: MATKIN, Mark, S.; US
HENDRICKSEN, Mark, W.; US
SHAURETTE, James, D.; US
LATWESEN, David, G.; US
GRZELAK, Keith, D.; US
Priority Data:
15/422,30701.02.2017US
Title (EN) NAND MEMORY ARRAYS, AND METHODS OF FORMING NAND MEMORY ARRAYS
(FR) MATRICES DE MÉMOIRE NAND ET PROCÉDÉS POUR FORMER DES MATRICES DE MÉMOIRE NAND
Abstract: front page image
(EN) Some embodiments include a NAND memory array which has a vertical stack of alternating insulative levels and wordline levels The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels, and is spaced form the control gate regions by charge-blocking material. The charge-trapping material along vertically adjacent wordline levels is spaced by intervening regions through which charge migration is impeded Channel material extends vertically along the stack and is spaced from the charge-trapping material by charge-tunneling material. Some embodiments include methods of forming NAND memory arrays.
(FR) Certains modes de réalisation comprennent un réseau de mémoire NAND qui présente une pile verticale comprenant en alternance des niveaux isolants et des niveaux de lignes de mots. Les niveaux de lignes de mots ont des bornes terminales correpondant à des zones de grille de commande. Un matériau de piégeage de charges est disposé le long des zones de grille de commande des niveaux de ligne de mots, et est espacé des zones de grille de commande par un matériau de blocage de charges. Le matériau de piégeage de charges disposé le long de niveaux de ligne de mots verticalement adjacents est espacé par des zones intermédiaires empêchant la migration des charges. Un matériau de canal s'étend verticalement le long de la pile et est espacé du matériau de piégeage de charges par un matériau de transfert des charges par effet tunnel. Certains modes de réalisation comprennent des procédés pour former des matrices de mémoire NAND.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)