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1. (WO2018143344) SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR MANUFACTURING DEVICE
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Pub. No.: WO/2018/143344 International Application No.: PCT/JP2018/003408
Publication Date: 09.08.2018 International Filing Date: 01.02.2018
IPC:
H01L 21/02 (2006.01) ,H01L 21/52 (2006.01) ,H01L 23/373 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
52
Mounting semiconductor bodies in containers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
373
Cooling facilitated by selection of materials for the device
Applicants:
三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 東京都千代田区丸の内二丁目7番3号 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors:
仲村 恵右 NAKAMURA, Keisuke; JP
吹田 宗義 SUITA, Muneyoshi; JP
今井 章文 IMAI, Akifumi; JP
倉橋 健一郎 KURAHASHI, Kenichiro; JP
品川 友宏 SHINAGAWA, Tomohiro; JP
松田 喬 MATSUDA, Takashi; JP
吉嗣 晃治 YOSHITSUGU, Koji; JP
柳生 栄治 YAGYU, Eiji; JP
西村 邦彦 NISHIMURA, Kunihiko; JP
Agent:
曾我 道治 SOGA, Michiharu; JP
梶並 順 KAJINAMI, Jun; JP
上田 俊一 UEDA, Shunichi; JP
Priority Data:
2017-01735202.02.2017JP
Title (EN) SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR MANUFACTURING DEVICE
(FR) PROCÉDÉ DE FABRICATION DE SEMICONDUCTEUR ET DISPOSITIF DE FABRICATION DE SEMICONDUCTEUR
(JA) 半導体製造方法および半導体製造装置
Abstract:
(EN) Provided is a semiconductor manufacturing device that can reduce the occurrence of damage to a diamond substrate during chemical bonding of the diamond substrate to a semiconductor substrate. The present invention is provided with: a lower substrate support stage for supporting the diamond substrate; an upper substrate support stage for supporting the semiconductor substrate; a support stage driver unit for moving the lower substrate support stage and the upper substrate support stage and causing the diamond substrate and the semiconductor substrate to be adhered to each other while pressure is applied in the thickness direction; and a second mechanism part that deforms the surface of the upper substrate support stage facing the lower substrate support stage such that the surface of the semiconductor substrate facing the diamond substrate is a parallel curved surface or a parallel surface with respect to the surface of the diamond substrate facing the semiconductor substrate.
(FR) L'invention concerne un dispositif de fabrication de semiconducteur qui peut réduire l'apparition de dommages à un substrat de diamant pendant la liaison chimique du substrat de diamant à un substrat semiconducteur. La présente invention comprend : un étage de support de substrat inférieur pour supporter le substrat de diamant; un étage de support de substrat supérieur pour supporter le substrat semiconducteur; une unité d'entrainement d'étage de support pour déplacer l'étage de support de substrat inférieur et l'étage de support de substrat supérieur et amener le substrat de diamant et le substrat semiconducteur à être collés l'un à l'autre pendant qu'une pression est appliquée dans le sens de l'épaisseur; et une seconde partie de mécanisme qui déforme la surface de l'étage de support de substrat supérieur faisant face à l'étage de support de substrat inférieur de telle sorte que la surface du substrat semiconducteur faisant face au substrat de diamant est une surface incurvée parallèle ou une surface parallèle par rapport à la surface du substrat de diamant faisant face au substrat semiconducteur.
(JA) ダイヤモンド基板と半導体基板とを化学的に結合させる際にダイヤモンド基板に破損が生じることを低減させることができる半導体製造装置を得る。ダイヤモンド基板を支持する下部基板支持台と、半導体基板を支持する上部基板支持台と、下部基板支持台および上部基板支持台を移動させて、ダイヤモンド基板と半導体基板とを厚さ方向について圧力が加えられた状態で密着させる支持台駆動部と、上部基板支持台における下部基板支持台に対向する面を、半導体基板におけるダイヤモンド基板に対向する面がダイヤモンド基板における半導体基板に対向する面に対して平行曲面または平行面となるように変形させる第2機構部とを備えている。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)