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1. (WO2018143050) SEMICONDUCTOR DEVICE
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Pub. No.: WO/2018/143050 International Application No.: PCT/JP2018/002276
Publication Date: 09.08.2018 International Filing Date: 25.01.2018
IPC:
H01L 29/78 (2006.01) ,H01L 29/06 (2006.01) ,H01L 29/739 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70
Bipolar devices
72
Transistor-type devices, i.e. able to continuously respond to applied control signals
739
controlled by field effect
Applicants:
株式会社デンソー DENSO CORPORATION [JP/JP]; 愛知県刈谷市昭和町1丁目1番地 1-1, Showa-cho, Kariya-city, Aichi 4488661, JP
Inventors:
宮田 征典 MIYATA Masanori; JP
高橋 茂樹 TAKAHASHI Shigeki; JP
住友 正清 SUMITOMO Masakiyo; JP
志賀 智英 SHIGA Tomofusa; JP
Agent:
特許業務法人ゆうあい特許事務所 YOU-I PATENT FIRM; 愛知県名古屋市中区錦一丁目6番5号 名古屋錦シティビル4階 Nagoya Nishiki City Bldg. 4F 1-6-5, Nishiki, Naka-ku, Nagoya-shi, Aichi 4600003, JP
Priority Data:
2017-01867203.02.2017JP
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置
Abstract:
(EN) This semiconductor device has an element part (1) and an outer peripheral part (2) surrounding the element part (1), wherein a deep layer (23) is formed more deeply in the outer peripheral part (2) than in a base layer (12). When the position which, in the deep layers (23), is closest to the element part (1) is a boundary position (K), the distance between the boundary position (K) and the position which is closest to the outer peripheral part (2) in an emitter region (16) into which first carriers can be injected is a first distance (L1), and the distance between the boundary position (K) and the position of a stepped part in a surface direction of a semiconductor substrate (10) in a collector layer (21) is a second distance (L2), the first distance (L1) and the second distance (L2) are adjusted so that a carrier density at the outer peripheral part (2) is decreased on the basis of the withstand voltage of the outer peripheral part (2), the withstand voltage having been decreased by the deep layer (23).
(FR) Ce dispositif à semi-conducteur comporte une partie d'élément (1) et une partie périphérique externe (2) entourant la partie d'élément (1), une couche profonde (23) étant formée plus profondément dans la partie périphérique externe (2) que dans une couche de base (12). Lorsque la position qui, dans les couches profondes (23), est la plus proche de la partie d'élément (1) est une position limite (K), la distance entre la position limite (K) et la position qui est la plus proche de la partie périphérique externe (2) dans une région émettrice (16) dans laquelle peuvent être injectés des premiers porteurs de charge est une première distance (L1), et la distance entre la position limite (K) et la position d'une partie étagée dans une direction de surface d'un substrat semi-conducteur (10) dans une couche de collecteur (21) est une seconde distance (L2), la première distance (L1) et la seconde distance (L2) sont ajustées de telle sorte qu'une densité de porteur au niveau de la partie périphérique externe (2) est réduite sur la base de la tension de tenue de la partie périphérique externe (2), la tension de tenue ayant été diminuée par la couche profonde (23).
(JA) 素子部(1)と、素子部(1)を取り囲む外周部(2)とを有し、外周部(2)にベース層(12)よりも深さが深くされたディープ層(23)が形成された半導体装置において、ディープ層(23)における最も素子部(1)側の位置を境界位置(K)とし、境界位置(K)と、第1キャリアが注入され得るエミッタ領域(16)のうちの最も外周部(2)側の位置との間の距離を第1距離(L1)とし、境界位置(K)と、コレクタ層(21)のうちの半導体基板(10)の面方向における端部の位置との間の距離を第2距離(L2)とすると、第1距離(L1)および第2距離(L2)をディープ層(23)によって低下した外周部(2)の耐圧に基づいて当該外周部(2)におけるキャリア密度が低下するように調整する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)