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1. (WO2018142976) CSP-TYPE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
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Pub. No.: WO/2018/142976 International Application No.: PCT/JP2018/001700
Publication Date: 09.08.2018 International Filing Date: 22.01.2018
IPC:
H01L 23/12 (2006.01) ,H01L 21/301 (2006.01) ,H01L 21/768 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
301
to subdivide a semiconductor body into separate parts, e.g. making partitions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
Applicants:
株式会社村田製作所 MURATA MANUFACTURING CO., LTD. [JP/JP]; 京都府長岡京市東神足1丁目10番1号 10-1, Higashikotari 1-chome, Nagaokakyo-shi, Kyoto 6178555, JP
Inventors:
坂井 宣夫 SAKAI Nobuo; JP
Agent:
特許業務法人 楓国際特許事務所 KAEDE PATENT ATTORNEYS' OFFICE; 大阪府大阪市中央区農人橋1丁目4番34号 1-4-34, Noninbashi, Chuo-ku, Osaka-shi, Osaka 5400011, JP
Priority Data:
2017-01700501.02.2017JP
Title (EN) CSP-TYPE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
(FR) DISPOSITIF À SEMICONDUCTEUR DE TYPE CSP ET SON PROCÉDÉ DE FABRICATION
(JA) CSP型半導体デバイスおよびその製造方法
Abstract:
(EN) A CSP-type semiconductor device (101) has a semiconductor substrate (1), a rewiring layer (2), and a protection film (3). The semiconductor substrate (1) has a first surface (S1), and a side surface (S31) orthogonal to the first surface (S1), and a functional element (10) is formed on the first surface (S1). The rewiring layer (2) is formed on the whole surface on the first surface (S1) of the semiconductor substrate (1), has a side surface (S32) continuous from the side surface (S31) of the semiconductor substrate (1), and includes wiring patterns (21A, 21B) connected to the functional element (10). The protection film (3) is formed of a fluorocarbon polymer film that is continuously formed from the side surface (S32) of the rewiring layer (2) to the side surface (S31) of the semiconductor substrate (1).
(FR) L'invention concerne un dispositif à semiconducteur de type CSP (101) comprenant un substrat semiconducteur (1), une couche de recâblage (2), et un film de protection (3). Le substrat semiconducteur (1) a une première surface (S1), et une surface latérale (S31) orthogonale à la première surface (S1), et un élément fonctionnel (10) est formé sur la première surface (S1). La couche de recâblage (2) est formée sur toute la surface sur la première surface (S1) du substrat semiconducteur (1), comporte une surface latérale (S32) continue à partir de la surface latérale (S31) du substrat semiconducteur (1), et comprend des motifs de câblage (21A, 21B) connectés à l'élément fonctionnel (10). Le film de protection (3) est formé d'un film polymère de fluorocarbone qui est formé en continu à partir de la surface latérale (S32) de la couche de recâblage (2) jusqu'à la surface latérale (S31) du substrat semiconducteur (1).
(JA) CSP型半導体デバイス(101)は、半導体基板(1)、再配線層(2)および保護膜(3)を有する。半導体基板(1)は第1面(S1)およびこの第1面(S1)に直交する側面(S31)を有し、第1面(S1)に機能素子(10)が形成されている。再配線層(2)は、半導体基板(1)の第1面(S1)上の全面に形成され、半導体基板(1)の側面(S31)から連続する側面(S32)を有し、機能素子(10)に接続された配線パターン(21A,21B)を含む。保護膜(3)は、再配線層(2)の側面(S32)から半導体基板(1)の側面(S31)にかけて連続的に形成されたフルオロカーボン重合膜により形成されている。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)